TNETE2004PBE datasheet(27/46 Pages) TI

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TNETE2004

MDIO-MANAGED QuadPHY

FOUR 10BASE-T PHYSICAL-LAYER INTERFACES

SPWS023D – OCTOBER 1996 – REVISED OCTOBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

TNETE2004 pin-polarity register – QuadPHY_ppol at 0x16

BYTE 1

BYTE 0

–

RESERVED

Figure 17. TNETE2004 Pin-Polarity Register – QuadPHY_ppol at 0x16

Table 13. TNETE2004 Pin-Polarity Register (QuadPHY_ppol at 0x16) Bit Functions

BIT

FUNCTION

DIRECTION†

NO.

NAME

FUNCTION

DIRECTION†

INV_CRS

Invert carrier sense. When INV_CRS is set to 1, carrier sense is indicated by a low voltage on the

appropriate CRSx pin. When INV_CRS is 0, carrier sense is indicated by a high voltage level.

R/W

INV_COL

Invert collision. When INV_COL is set to 1, a collision is indicated by a low voltage on the

appropriate COLx pin. When INV_COL is 0, collision is indicated by a high voltage level.

R/W

INV_RXCLK

Invert RXCLK. When INV_RXCLK is set to 1, the MAC samples RXD data on the falling edge of

RXCLK. When INV_RXCLK is 0, data is sampled on the rising edge of RXCLK.

R/W

INV_TXCLK

Invert TXCLK. When INV_TXCLK is set to 1, the TNETE2004 samples data on its TXD pins on

the falling edges of TXCLK. When INV_TXCLK is set to 0, the data is sampled on the rising edges

of TXCLK.

R/W

INV_TXEN

Invert TXEN. When INV_TXEN is set to 1, the MAC indicates that data is to be transmitted by

forcing the appropriate TXENx pin low. When INV_TXEN is 0, valid data is indicated by a high

voltage level.

R/W

RXD_POL

Receive data active-low. When RXD_POL is set to 1, RXD is driven low when no data is being

received by the PHY. When RXD_POL is set to 0, RXD is driven high when no data is being

received.

R/W

RXCLK_OFF

Receive clock off when inactive. When RXCLK_OFF is set to 1, RXCLK outputs seven more clock

cycles after CRS is inactive and then RXCLK is held high. Otherwise, RXCLK continuously

outputs a 10-MHz clock signal.

R/W

8–0

RESERVED

Reserved. Read as 0.

† RO = read only, R/W = read/write

After power on or a reset prior to writing to this register, the polarity of CRS, COL, TXEN, RXCLK, and TXCLK

is determined by CMODE0 and CMODE1. After this register has been written to, CMODE has no effect on the

polarity. This register is always read as 0 until it has been written to.

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