TNETE2004

MDIO-MANAGED QuadPHY

FOUR 10BASE-T PHYSICAL-LAYER INTERFACES

SPWS023D – OCTOBER 1996 – REVISED OCTOBER 1997

31

POST OFFICE BOX 655303

mode 4 receive-data timing

MIN

TYP

MAX

UNIT

tRDLAT

Receive-data latency

500

ns

tPD

Receive data

40

60

ns

tCRSHO

Time from receive idle to carrier sense off

200

ns

RCVP/

RCVN

RXCLK

(see Note A)

CRS

tRDLAT

tCRSHO

tPD

RXD

(see Note B)

NOTES: A. RXCLK is continuous.

B. During a collision, the data output on RXD is not valid received data (or looped-back transmit data) since the digital PLL is acquiring

lock to a different source of incoming data.

Figure 21. Mode 4 Receive Timing

transmit-data timings

To be transmitted, data must be valid and synchronized with the appropriate edge of TXCLK according to the

selected compatibility mode (see Table 2). Figure 22 through Figure 25 show timing for modes of operation. The

only differences in modes are the polarity changes in RXD (during CRS deasserted), TXEN, RXCLK, and CRS.

In half-duplex operation, transmit data is internally looped back to the receive data pins through the receiver

circuitry. The following timing table shows transmit data timing.

modes 1–4 transmit-data timing

MIN

TYP

MAX

UNIT

tENSU

Setup time, transmit enable

50

ns

tSUD

Transmit startup delay

150

ns

tCRSON

Time to CRS assertion

150

ns

tTDSU

Setup time, transmit data

25

ns

tTDHO

Hold time, transmit data

2.5

ns

tTDLAT

Transmit-data latency

100

ns

tTFIN

Time to transmit idle

400

ns

tLOOP

Loopback latency

500

ns