November 2006

ASM2P2310A

rev 0.3

Notice: The information in this document is subject to change without notice.

PulseCore Semiconductor Corporation

1715 S. Bascom Ave Suite 200, Campbell, CA 95008

• Tel: 408-879-9077 • Fax: 408-879-9018

www.pulsecoresemi.com

2.5-V TO 3.3-V High-Performance Clock Buffer

Features

• High-Performance 1:10 Clock Driver for General Purpose

applications. Operates up to 200 MHz at 3.3V Supply

Voltage

• Pin-to-Pin Skew < 100 pS at 3.3V Supply Voltage

• Supply Range : 2.3V to 3.6V

• Operating Temperature Range : -40°C to 85°C

• Output Enable Glitch Suppression

• Distributes One Clock Input to Two Banks of Five

Outputs

• 25Ω On Chip Series Damping Resistors

• Packaged in 24 Pin TSSOP Package

Block Diagram

Product Description

The ASM2P2310A is a high-performance, low-skew clock

buffer that operates up to 200MHz. Two banks of five

outputs each provide low-skew copies of CLK. After power

up, the default state of the outputs is low regardless of the

state of the control pins. For normal operation, the outputs

of bank 1Y[0:4] or 2Y[0:4] can be placed in a low state

when the control pins (1G or 2G, respectively) are held low

and a negative clock edge is detected on the CLK input.

The outputs of bank 1Y[0:4] or 2Y[0:4] can be switched into

the buffer mode when the control pins (1G and 2G) are

held high and a negative clock edge is detected on the CLK

input. The device operates in a 2.5V and 3.3V environment.

The built-in output enable glitch suppression ensures a

synchronized output enable sequence to distribute full

period clock signals.

The ASM2P2310A is characterized for operation from

-40°C to 85°C.

1G

25Ω

25Ω

25Ω

25Ω

25Ω

3

4

5

8

9

1Y4

1Y3

1Y2

1Y1

1Y0

11

LOGIC CONTROL

25Ω

25Ω

25Ω

25Ω

25Ω

21

20

17

16

12

2Y4

2Y3

2Y2

2Y1

2Y0

24

CLK

LOGIC CONTROL

13

2G