November 2006

ASM2P2310A

rev 0.3

2.5-V TO 3.3-V High-Performance Clock Buffer

2 of 11

Notice: The information in this document is subject to change without notice.

Pin Configuration

Pin Description

Pin #

Pin Name

Type

Description

1

GND

P

Ground Pin

2

P

DC Power supply, 2.3 V – 3.6V

3

1Y0

O

Buffered Output Clock

4

1Y1

O

Buffered Output Clock

5

1Y2

O

Buffered Output Clock

6

GND

P

Ground Pin

7

GND

P

Ground Pin

8

1Y3

O

Buffered Output Clock

9

1Y4

O

Buffered Output Clock

10

P

DC power supply, 2.3V – 3.6V

11

1G

I

Output enable control for 1Y[0:4] outputs. This output enable is active-high,

meaning the 1Y[0:4] clock outputs follow the input clock (CLK) if this pin is logic

high.

12

2Y4

O

Buffered Output Clock

13

2G

I

Output enable control for 2Y[0:4] outputs. This output enable is active-high,

meaning the 2Y[0:4] clock outputs follow the input clock (CLK) if this pin is logic

high.

14

P

DC power supply, 2.3V – 3.6V

15

P

DC power supply, 2.3V – 3.6V

16

2Y3

O

Buffered Output Clock

17

2Y2

O

Buffered Output Clock

18

GND

P

Ground Pin

19

GND

P

Ground Pin

20

2Y1

O

Buffered Output Clock

21

2Y0

O

Buffered Output Clock

22

P

DC power supply, 2.3V – 3.6V

23

P

DC power supply, 2.3V – 3.6V

24

CLK

I

Input reference frequency

GND

GND

2

23

9

16

10

15

1

24

3

22

4

21

5

20

6

19

7

18

8

17

11

14

12

13

GND

1G

2Y0

CLK

2G

2Y1

2Y2

2Y3

GND

GND

1Y2

1Y0

1Y1

1Y3

1Y4

2Y4

ASM2P2310A