System description

STA2064

10/19

Doc ID 16057 Rev 1

MHz. The same divisor will be from 2 to 16 when the PLL2 is running at 432 MHz, giving an

operating frequency in the range from 216 to 27 MHz.

The GPS baseband clock will be derived from the MCLK clock with a divider, internal to the

subsytem, by 1, 2,3 or 4, under ARM11 control. RFCLK is the clock received from the RF

front-end chip.

2.7.2

Touchscreen controller/ADC

STA2064 embeds a 4-wire Touch Screen Controller. The Touch Screen Controller main

characteristics are:

●

Active Window Clip

●

Movements Tracking

●

12-bit SAR ADC resolution when used for Touch screen (with averaging)

●

Measurement oversampling from 2 to 8

●

Up to 128 coordinates FIFO, with programmable FIFO threshold

●

ADC minimum conversion time of 1

μs

●

Capability to support 4 additional analog inputs for auxiliary functions like battery

voltage monitoring and accessory control.

The ADC of the Touch Screen Controller can be also used for the conversion of external

analog signals. In this case the ADC has a 10-bit resolution (its native resolution).

2.7.3

Multisupply IO ring

STA2064 has multivoltage IOs capable of supporting 1.8V, 2.5V or 3.3V interfaces. The

rings are defined as follows:

●

A: All peripherals with exception of what belongs to other rings

●

B: LCD

●

C: DRAM

●

E: MMC1 (GPIO40-47, GPIO76-82), CAN0

The default voltage applied to each ring will be at reset time will be:

●

A: 1.8V

●

B: 1.8V

●

C: 1.8V

●

E: 3.3V