System description

STA2065

6/20

Doc ID16050 Rev 1

2.3.6

Real-time clock (RTC)

The RTC provides a one second resolution clock. This keeps time when the system is

inactive and can be used to wake the system up when a programmed ‘alarm’ time is

reached. It has a clock trimming feature to compensate the drift of the 32.768 kHz crystal.

2.3.7

Real-time timer (RTT)

The RTT has the possibility of being clocked off. This reduces the always_on domain

consumption during Deep Sleep. By default the RTT has its clock enabled.

2.3.8

Always_ON supply

lowest consumption possible, can also be configured as low as 1.0 ±10%V when the device

is in deep-sleep.

2.3.9

Enhanced function timer (EFT)

STA2065 features 4 16-bit EFTs. Each of the four EFT timers has a 16-bit free-running

counter with 7-bit prescaler, up to two input capture/output compare functions, a pulse

counter function, and a PWM channel with selectable frequency.

2.3.10

Watchdog timer (WDT)

This OS resource is used to trigger a system reset in the event of software failure.

2.4

Memory interfaces

2.4.1

Flexible static memory controller (FSMC)

The flexible static memory controller (FSMC) supports, with two chip selects:

●

ROM

●

Static RAM

●

NOR type flash memories, not multiplexed

●

NOR type flash memories, multiplexed

It also supports, with two additional separate chip selects:

●

NAND type flash memories, SLC small or large page

●

NAND type flash memories, MLC

For NAND type of memories, the FSMC has been enhanced to implement an error

correction in hardware, based on the Bose-Chaudhuri-Hocquenghem (BCH) code, able to

correct up to 8-bit over 512 bytes+syndrome. The BCH code will calculate, in hardware, the

syndrome only. The actual correction will be implemented through S/W intervention.