STA2065

System features introduction

Doc ID16050 Rev 1

13/20

3

System features introduction

In this chapter, an introduction to the main STA2065 system features is given. These will be

explained in detail later in this document.

3.1

Power region partition

STA2065 is a device targeted to wide range of applications, starting from handheld battery

powered devices thanks to an optimzed power management but also addressing in dash

automotive power requirements thanks to its flexibile multivoltage IO.

Three main power regions are identified:

●

Management Unit), SRC (System Clock and Reset controller) and the Backup RAM of

mode. For this reason, the static power consumption of this region stays below 20uA

worst case.

●

at the same voltage. A maximum of 10% variation between the two regions is required.

●

groups and each of them can be powered at different, independent voltages. Some

groups may have specific constraint in terms of power voltage range in order to meet

specific electrical characteristic compliant to some standards; some of these groups

are, for example, in the DDR interface and the 1.1 embedded USB transceiver. There is

(also in the lowest power consumption state of STA2065) in order to make the wake-up

state. For more information, please refer to Chapter 3.6: IO groups on page 17.

3.2

Frequency region partition

STA2065 is designed so that there are two PLLs. PLL1 generates clock frequencies for the

ARM core and the internal buses, while the PLL2 generates clock frequencies for each

peripheral kernel and also for each peripheral interface. This means that each peripheral

receives the clock derived from the PLL1 at its internal interface, then it works with the clock

derived from the PLL2. Despite the use of two PLLs, a single system clock input or a single

external crystal is needed (in addition to the RTC clock (or crystal)).