STA2065

System description

Doc ID16050 Rev 1

7/20

2.4.2

SD/MMC

STA2065 features three SD/SDIO/MMC interfaces up to 52 MHz / 8-bit. The main clock

available to the peripherals is:

●

PLL2CLK/13 (when PLL2CLK is 624 MHz and SRC_MMC52 = 0, 48 MHz will be

generated)

●

PLL2CLK/12 (when PLL2CLK is 624 MHz and SRC_MMC = 1, 52 MHz will be

generated)

●

PLL2CLK/9 (when PLL2CLK is 432 MHz, 48 MHz will be generated)

The peripheral is compliant to the following standards:

●

MMC 4.4

●

SD 2.0/Part 1 - Physical Layer

●

SD 2.0/Part E1 - SDIO Specification

2.4.3

DDR-SDRAM controller

The SDRAM controller has been designed to support up to 1Gbit over each of the two chip

selects (or up to 2 Gbit over a single chip select) of:

●

LP DDR-SDRAM

●

DDR2

The memory data bus will be 16 or 32-bit wide for LP DDR-SDRAM memories (under

software control). This same configuration is also supported for DDR2 type of memories,

with two 16-bit devices per chip select.

2.4.4

Smartcard interface

STA2065 features a smartcard interface compliant to the standard ISO7816-3.

STA2065 supports 3.0V or 1.8V type of Cards.

2.5

Audio/video functions

2.5.1

C3

It is composed of CD-ROM Decoder Block, responsible for performing sector descrambling

Form1, and Data Filter block supporting frame data filtering and different block layout

organization possibilities. The C3 block can take its input data directly from SPDIF or from

the memory space, and delivers back its output data to memory, supporting DMA requests.