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CDK2000 数据表(PDF) 14 Page - Cirrus Logic

部件名 CDK2000
功能描述  Fractional-N Frequency Synthesizer
PDF  24 Pages
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制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

CDK2000 数据表(HTML) 14 Page - Cirrus Logic

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CS2200-OTP
14
DS842F1
5.5
Auxiliary Output
The auxiliary output pin (AUX_OUT) can be mapped, as shown in Figure 8, to one of three signals: refer-
ence clock (RefClk), additional PLL clock output (CLK_OUT), or a PLL lock indicator (Lock). The mux is con-
trolled via the AuxOutSrc[1:0] modal parameter. If AUX_OUT is set to Lock, the AuxLockCfg global
parameter is then used to control the output driver type and polarity of the LOCK signal (see section 6.3.1
on page 18). If AUX_OUT is set to CLK_OUT, the phase of the PLL Clock Output signal on AUX_OUT may
differ from the CLK_OUT pin. The driver for the pin can be set to high-impedance using the M2 pin when
the M2Config[1:0] global parameter is set to either 001 or 010.
Figure 8. Auxiliary Output Selection
5.6
Mode Pin Functionality
5.6.1
M1 and M0 Mode Pin Functionality
M[1:0] determine the functional mode of the device and select both the default User Defined Ratio and
the set of modal parameters. The modal parameters are RModSel[1:0] and AuxOutSrc[1:0]. By modifying
one or more of the modal parameters between the 4 sets, different functional configurations can be
achieved. However, global parameters are fixed and the same value will be applied to each functional
configuration. Figure 10 on page 17 provides a summary of all parameters used by the device.
Referenced Control
Parameter Definition
AuxOutSrc[1:0]...................... “Auxiliary Output Source Selection (AuxOutSrc[1:0])” on page 18
AuxOutDis .............................“M2 Configured as Output Disable” on page 15
AuxLockCfg........................... “AUX PLL Lock Output Configuration (AuxLockCfg)” section on page 18
M2Config[2:0]........................“M2 Pin Configuration (M2Config[2:0])” on page 19
3:1 Mux
Auxiliary Output Pin
(AUX_OUT)
AuxOutDis
AuxOutSrc[1:0]
AuxLockCfg
Timing Reference Clock
(RefClk)
PLL Clock Output
(PLLClkOut)
PLL Lock/Unlock Indication
(Lock)



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