SRAM

SRAM

SRAM

SRAM

SRAM

MT5C1001

Limited Availability

MT5C1001

Rev. 2.1 06/05

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

1

Austin Semiconductor, Inc.

FEATURES

• High Speed: 20, 25, 35, and 45

• Battery Backup: 2V data retention

• Low power standby

• Single +5V (+10%) Power Supply

• Easy memory expansion with CE\ and OE\ options.

• All inputs and outputs are TTL compatible

• Three-state output

OPTIONS

MARKING

• Timing

20ns access

-20

25ns access

-25

35ns access

-35

45ns access

-45

55ns access

-55*

70ns access

-70*

• Package(s)

Ceramic DIP (400 mil)

C

No. 109

Ceramic LCC

EC

No. 207

Ceramic Flatpack

F

No. 303

Ceramic SOJ

DCJ

No. 501

• Operating Temperature Ranges

IT

XT

• 2V data retention/low power

L

*Electrical characteristics identical to those provided for the

45ns access devices.

PIN ASSIGNMENT

(Top View)

AVAILABLE AS MILITARY

SPECIFICATIONS

• SMD 5962-92316

• MIL-STD-883

28-Pin DIP (C)

(400 MIL)

32-Pin LCC (EC)

32-Pin SOJ (DCJ)

32-Pin Flat Pack (F)

GENERAL DESCRIPTION

The MT5C1001 employs low power, high-performance

silicon-gate CMOS technology. Static design eliminates the

need for external clocks or timing strobes while CMOS circuitry

reduces power consumption and provides for greater

reliability.

For flexibility in high-speed memory applications, ASI

offers chip enable (CE\) and output enable (OE\) capability.

These enhancements can place the outputs in High-Z for addi-

tional flexibility in system design. Writing to these devices is

accomplished when write enable (WE|) and CE\ inputs are both

LOW. Reading is accomplished when WE\ remains HIGH while

CE\ and OE\ go LOW. The devices offer a reduced power

standby mode when disabled. This allows system designs to

achieve low standby power requirements.

The “L” version provides an approximate 50 percent

reduction in CMOS standby current (I

SBC2

) over the standard

version.

All devices operation from a single +5V power supply

and all inputs and outputs are fully TTL compatible.

1M x 1 SRAM

SRAM MEMORY ARRAY

For more products and information

please visit our web site at

www.austinsemiconductor.com

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

A10

A11

A12

A13

A14

A15

NC

A16

A17

A18

A19

Q

WE\

Vss

Vcc

A9

A8

A7

A6

A5

A4

NC

A3

A2

A1

A0

D

CE\

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

A10

A11

A12

NC

A13

A14

A15

NC

A16

A17

A18

A19

NC

Q

WE\

Vss

Vcc

NC

A9

A8

A7

A6

A5

A4

A3

NC

A2

NC

A1

A0

D

CE\

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

A10

A11

A12

NC

A13

A14

A15

NC

A16

A17

A18

A19

NC

Q

WE\

Vss

Vcc

NC

A9

A8

A7

A6

A5

A4

A3

NC

A2

NC

A1

A0

D

CE\