AD8120ACPZ-R2 datasheet(4/16 Pages) AD

4 / 16 page

AD8120

Rev. 0 | Page 4 of 16

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

DIGITAL CONTROL INPUT CHARACTERISTICS

SDO/SDA, SCK/SCL, SDI/A1, CS/A0, SER_SEL,

MODE

Input Bias Current

μA

Input High Voltage

2.6

Input Low Voltage

0.6

Output High Voltage

4.5

Output Low Voltage

0.6

SPI TIMING CHARACTERISTICS

Clock Frequency

SCK

MHz

CS Setup Time, t1

CS to SCK

Clock Pulse High, t2

SCK

Clock Pulse Low, t3

SCK

Data Setup Time, t4

SDI to SCK

Data Hold Time, t5

SDI to SCK

CS Hold Time, t6

SCK to CS

I2C TIMING CHARACTERISTICS

Clock Frequency

SCL

100

kHz

Start Setup Time, t1

SDA to SCL

Clock Pulse High, t2

SCL

μs

Clock Pulse Low, t3

SCL

μs

Data Setup Time, t4

SDA (input) to SCL

100

Data Hold Time, t5

SDA (input) to SCL

100

Hold Time, t6

SCL to SDA

POWER SUPPLY

Positive Supply Range

4.5

5.5

Negative Supply Range

−5.5

−4.5

Positive Quiescent Current

Delay = 0 ns

Delay = 50 ns

114

Powered down, PD low

Negative Quiescent Current

Delay = 0 ns

Delay = 50 ns

108

Powered down, PD low

0.5

Quiescent Current Drift

TMIN to TMAX, delay = 0 ns

0.13

mA/°C

TMIN to TMAX, delay = 50 ns

0.36

mA/°C

+PSRR

RL = 150 Ω, delay = 50 ns

−PSRR

RL = 150 Ω, delay = 50 ns

AD8120ACPZ-R2 数据表(PDF) 4 Page - Analog Devices

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