STM32F102C4T6ATR datasheet(68/69 Pages) STMICROELECTRONICS

68 / 69 page

Revision history

STM32F102x4, STM32F102x6

68/69

Doc ID 15057 Rev 3

Revision history

Table 53.

Document revision history

Date

Revision

Changes

23-Sep-2008

Initial release.

09-Apr-2009

I/O information clarified on page 1. Figure 1: STM32F102xx low-density

USB access line block diagram and Figure 5: Memory map modified.

In Table 4: low-density STM32F102xx pin definitions: PB4, PB13, PB14,

PB15, PB3/TRACESWO moved from Default column to Remap column,

Note 4 added.

PD value added for LQFP64 package in Table 8: General operating

conditions.

Note modified in Table 12: Maximum current consumption in Run mode,

code with data processing running from Flash and Table 14: Maximum

current consumption in Sleep mode, code running from Flash or RAM.

Figure 13, Figure 14 and Figure 15 show typical curves.

Figure 27: ADC accuracy characteristics modified.

Figure 29: Power supply and reference decoupling modified. Small text

changes.

Table 19: High-speed external user clock characteristics and Table 20:

Low-speed external user clock characteristics modified.

ACCHSI max values modified in Table 23: HSI oscillator characteristics.

24-Sep-2009

Note 5 updated and Note 4 added in Table 4: low-density STM32F102xx

pin definitions. Typical IDD_VBAT value added in Table 15: Typical and

maximum current consumptions in Stop and Standby modes. Figure 12:

Typical current consumption on VBAT with RTC on versus temperature at

different VBAT values added.

fHSE_ext min modified in Table 19: High-speed external user clock

characteristics.

CL1 and CL2 replaced by C in Table 21: HSE 4-16 MHz oscillator

characteristics and Table 22: LSE oscillator characteristics (fLSE =

32.768 kHz), notes modified and moved below the tables. Table 23: HSI

oscillator characteristics modified. Conditions removed from Table 25:

Low-power mode wakeup timings.

Note 1 modified below Figure 18: Typical application with an 8 MHz

crystal.

Figure 21: Recommended NRST pin protection modified.

IEC 1000 standard updated to IEC 61000 and SAE J1752/3 updated to

IEC 61967-2 in Section 5.3.10: EMC characteristics on page 44.

Jitter added to Table 26: PLL characteristics.

CADC and RAIN parameters modified in Table 44: ADC characteristics.

RAIN max values modified in Table 45: RAIN max for fADC = 12 MHz.

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