数据搜索系统，热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

预览 PDF HTML

25LC080C 数据表(PDF) 8 Page - Microchip Technology

部件名 25LC080C
功能描述  8K-256K SPI Serial EEPROM High Temp Family Data Sheet
PDF  24 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

25LC080C 数据表(HTML) 8 Page - Microchip Technology

Back Button 25LC080C Datasheet HTML 4Page - Microchip Technology 25LC080C Datasheet HTML 5Page - Microchip Technology 25LC080C Datasheet HTML 6Page - Microchip Technology 25LC080C Datasheet HTML 7Page - Microchip Technology 25LC080C Datasheet HTML 8Page - Microchip Technology 25LC080C Datasheet HTML 9Page - Microchip Technology 25LC080C Datasheet HTML 10Page - Microchip Technology 25LC080C Datasheet HTML 11Page - Microchip Technology 25LC080C Datasheet HTML 12Page - Microchip Technology Next Button
Zoom Inzoom in Zoom Outzoom out
 8 / 24 page
background image
25LCXXX
DS22131C-page 8
Preliminary
© 2009 Microchip Technology Inc.
3.0
FUNCTIONAL DESCRIPTION
3.1
Principles of Operation
The 25LCXXX are Mid-Density Serial EEPROMs
designed to interface directly with the Serial Peripheral
Interface (SPI) port of many of today’s popular micro-
controller families, including Microchip’s PIC® micro-
controllers. It may also interface with microcontrollers
that do not have a built-in SPI port by using discrete I/
O lines programmed properly in firmware to match the
SPI protocol.
The 25LCXXX contains an 8-bit instruction register.
The device is accessed via the SI pin, with data being
clocked in on the rising edge of SCK. The CS pin must
be low and the HOLD pin must be high for the entire
operation.
Table 3-1 contains a list of the possible instruction
bytes and format for device operation. All instructions,
addresses, and data are transferred MSB first, LSB
last.
Data (SI) is sampled on the first rising edge of SCK
after CS goes low. If the clock line is shared with other
peripheral devices on the SPI bus, the user can assert
the HOLD input and place the 25LCXXX in ‘HOLD’
mode. After releasing the HOLD pin, operation will
resume from the point when the HOLD was asserted.
Block Diagram
SI
SO
SCK
CS
HOLD
WP
STATUS
Register
I/O Control
Memory
Control
Logic
X
Dec
HV Generator
EEPROM
Array
Page Latches
Y Decoder
Sense Amp.
R/W Control
Logic
VCC
VSS
TABLE 3-1:
INSTRUCTION SET
Instruction Name
Instruction Format
Description
READ
0000 0011
Read data from memory array beginning at selected address
WRITE
0000 0010
Write data to memory array beginning at selected address
WRDI
0000 0100
Reset the write enable latch (disable write operations)
WREN
0000 0110
Set the write enable latch (enable write operations)
RDSR
0000 0101
Read STATUS register
WRSR
0000 0001
Write STATUS register



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com