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25LC080C 数据表(PDF) 13 Page - Microchip Technology |
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25LC080C 数据表(HTML) 13 Page - Microchip Technology |
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13 / 24 page  © 2009 Microchip Technology Inc. Preliminary DS22131C-page 13 25LCXXX 3.6 Write Status Register Instruction (WRSR) The Write Status Register instruction (WRSR) allows the user to write to the nonvolatile bits in the STATUS register as shown in Table 3-2. The user is able to select one of four levels of protection for the array by writing to the appropriate bits in the STATUS register. The array is divided up into four segments. The user has the ability to write-protect none, one, two or all four of the segments of the array. The partitioning is controlled as shown in Table 3-3. The Write-Protect Enable (WPEN) bit is a nonvolatile bit that is available as an enable bit for the WP pin. The Write-Protect (WP) pin and the Write-Protect Enable (WPEN) bit in the STATUS register control the programmable hardware write-protect feature. Hard- ware write protection is enabled when WP pin is low and the WPEN bit is high. Hardware write protection is disabled when either the WP pin is high or the WPEN bit is low. When the chip is hardware write-protected, only writes to nonvolatile bits in the STATUS register are disabled. See Table 5-1 for a matrix of functionality on the WPEN bit. See Figure 3-7 for the WRSR timing sequence. TABLE 3-3: ARRAY PROTECTION TABLE 3-4: ARRAY PROTECTED ADDRESS LOCATIONS FIGURE 3-7: WRITE STATUS REGISTER TIMING SEQUENCE (WRSR) BP1 BP0 Array Addresses Write-Protected Array Addresses Unprotected 00 None All 01 Upper 1/4 Lower 3/4 10 Upper 1/2 Lower 1/2 11 All None Density Upper 1/4 Upper 1/2 All 8K 300h - 3FFh 200h - 3FFh 000h - 3FFh 16K 600h - 7FFh 400h - 7FFh 000h - 7FFh 32K C00h - FFFh 800h - FFFh 000h - FFFh 64K 1800h - 1FFFh 1000h - 1FFFh 0000h - 1FFFh 128K 3000h - 3FFFh 2000h - 3FFFh 0000h - 3FFFh 256K 6000h - 7FFFh 4000h - 7FFFh 0000h - 7FFFh SO SI CS 9 1011 12131415 0 1 0 0 0 0 00 76 5 4 21 0 Instruction Data to STATUS Register High-Impedance SCK 0 2 34 56 7 1 8 3 Note: An internal write cycle (TWC) is initiated on the rising edge of CS after a valid write STATUS register sequence. |
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