MCP6566UT-ESLASHMS datasheet(17/44 Pages) MICROCHIP

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DS22143B-page 17

MCP6566/6R/6U/7/9

4.0

APPLICATIONS INFORMATION

The MCP6566/6R/6U/7/9 family of open-drain output

comparators are fabricated on Microchip’s state-of-

the-art CMOS process. They are suitable for a wide

range of high speed applications requiring low power

consumption.

4.1

Comparator Inputs

4.1.1

NORMAL OPERATION

The input stage of this family of devices uses two

differential input stages in parallel. This configuration

provides three regions of operation, one operates at

low input voltages, one at high input voltages, and one

at mid input voltage. With this topology, the input

voltage range is 0.3V above VDD and 0.3V below VSS,

while providing low offset voltage through out the

common mode range. The input offset voltage is

measured at both VSS - 0.3V and VDD + 0.3V to ensure

proper operation.

The MCP6566/6R/6U/7/9 family has internally-set

hysteresis VHYST that is small enough to maintain input

offset accuracy and large enough to eliminate output

chattering caused by the comparator’s own input noise

voltage ENI. Figure 4-1 depicts this behavior. Input

offset voltage (VOS) is the center (average) of the

(input-referred) low-high and high-low trip points. Input

hysteresis voltage (VHYST) is the difference between

the same trip points.

FIGURE 4-1:

The MCP6566/6R/6U/7/9

comparators’ internal hysteresis eliminates

output chatter caused by input noise voltage.

4.1.2

INPUT VOLTAGE AND CURRENT

LIMITS

The ESD protection on the inputs can be depicted as

shown in Figure 4-2. This structure was chosen to

protect the input transistors, and to minimize input bias

current (IB). The input ESD diodes clamp the inputs

when they try to go more than one diode drop below

VSS. They also clamp any voltages that go too far

above VDD; their breakdown voltage is high enough to

allow normal operation, and low enough to bypass ESD

events within the specified limits.

FIGURE 4-2:

Simplified Analog Input ESD

Structures.

In order to prevent damage and/or improper operation

of these amplifiers, the circuits they are in must limit the

currents (and voltages) at the VIN+ and VIN– pins (see

Section 1.1 “Maximum Ratings*” at the beginning of

Section 1.0 “Electrical Characteristics”). Figure 4-3

shows the recommended approach to protecting these

inputs. The internal ESD diodes prevent the input pins

(VIN+ and VIN–) from going too far below ground, and

the resistors R1 and R2 limit the possible current drawn

out of the input pin. Diodes D1 and D2 prevent the input

pin (VIN+ and VIN–) from going too far above VDD.

When implemented as shown, resistors R1 and R2 also

limit the current through D1 and D2.

FIGURE 4-3:

Protecting the Analog

Inputs.

-3

-2

-1

Time (100 ms/div)

-30

-25

-20

-15

-10

-5

VOUT

VIN–

VDD = 5.0V

Hysteresis

Bond

Pad

Bond

Pad

Bond

Pad

VDD

VIN+

VSS

Input

Stage

Bond

Pad

VIN–

VDD

R2 ≥

VSS – (minimum expected V2)

2mA

VOUT

–

R1 ≥

VSS – (minimum expected V1)

2mA

VPU

MCP656X

MCP6566UT-E/MS 数据表(PDF) 17 Page - Microchip Technology

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