MPC8533VTARJB datasheet(34/116 Pages) FREESCALE

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MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3

Freescale Semiconductor

Enhanced Three-Speed Ethernet (eTSEC), MII Management

A timing diagram for TBI receive appears in Figure 17.

Figure 17. TBI Single-Clock Mode Receive AC Timing Diagram

8.5.4

RGMII and RTBI AC Timing Specifications

Table 32 presents the RGMII and RTBI AC timing specifications.

Table 32. RGMII and RTBI AC Timing Specifications

At recommended operating conditions with L/TVDD of 2.5 V ± 5%.

Parameter/Condition

Symbol1

Min

Typ

Max

Unit

Notes

Data to clock output skew (at transmitter)

tSKRGT_TX

–500

500

Data to clock input skew (at receiver)

tSKRGT_RX

1.0

—

2.8

Clock period duration

tRGT

7.2

8.0

8.8

Duty cycle for 10BASE-T and 100BASE-TX

tRGTH/tRGT

3, 4

Rise time (20%–80%)

tRGTR

—

0.75

Fall time (20%–80%)

tRGTF

—

0.75

Notes:

1. In general, the clock reference symbol representation for this section is based on the symbols RGT to represent RGMII and

RTBI timing. For example, the subscript of tRGT represents the TBI (T) receive (RX) clock. Note also that the notation for rise

(R) and fall (F) times follows the clock symbol that is being represented. For symbols representing skews, the subscript is

skew (SK) followed by the clock that is being skewed (RGT).

2. This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns

will be added to the associated clock signal.

3. For 10 and 100 Mbps, tRGT scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.

4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as

long as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed

transitioned between.

5. Guaranteed by design.

RX_CLK

RCG[9:0]

Valid Data

tTRRR

tTRRF

tTRRDV

tTRR

tTRRH

tTRRDX

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