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MPC8378CVRALDA 数据表(PDF) 31 Page - Freescale Semiconductor, Inc

部件名 MPC8378CVRALDA
功能描述  PowerQUICC??II Pro Processor Hardware Specifications
PDF  126 Pages
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制造商  FREESCALE [Freescale Semiconductor, Inc]
网页  http://www.freescale.com
标志 FREESCALE - Freescale Semiconductor, Inc

MPC8378CVRALDA 数据表(HTML) 31 Page - Freescale Semiconductor, Inc

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MPC8378E PowerQUICCII Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
31
Ethernet: Enhanced Three-Speed Ethernet (eTSEC)
8.3.3.2
MII Receive AC Timing Specifications
Table 31 provides the MII receive AC timing specifications.
Figure 12 provides the AC test load for eTSEC.
Figure 12. eTSEC AC Test Load
Table 31. MII Receive AC Timing Specifications
At recommended operating conditions with LVDD of 3.3 V ± 5%.
Parameter
Symbol 1
1
The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII receive
timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference (K) going
to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data input signals
(D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. Note that, in general, the
clock reference symbol representation is based on three letters representing the clock of a particular functional. For example,
the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the
appropriate letter: R (rise) or F (fall).
Min
Typical
Max
Unit
Input low voltage
VIL
——
0.7
V
Input high voltage
VIH
1.9
V
RX_CLK clock period 10 Mbps
tMRX
400
ns
RX_CLK clock period 100 Mbps
tMRX
—40
ns
RX_CLK duty cycle
tMRXH/tMRX
35
65
%
RXD[3:0], RX_DV, RX_ER setup time to RX_CLK
tMRDVKH
10.0
ns
RXD[3:0], RX_DV, RX_ER hold time to RX_CLK
tMRDXKH
10.0
ns
RX_CLK clock rise (20%-80%)
tMRXR
1.0
4.0
ns
RX_CLK clock fall time (80%-20%)
tMRXF
1.0
4.0
ns
Note:
Output
Z0 = 50 Ω
LVDD/2
RL = 50 Ω



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