DA6501.001

27 October 2008

5 (16)

MAS6501 CONTROL REGISTER

Table 1. MAS6501 control register bit description

Bit Number

Bit Name

Description

Value

Function

7-6

OSRS(1:0)

Over Sampling Ratio

(OSR) selection

11

01

10

00

OSR = 512

OSR = 256

OSR = 128

OSR = 64

5

SCO

Start Conversion

0

1

No Conversion

Start Conversion

4

PTS

Pressure/Temperature

Selection

1

0

Pressure configuration

Temperature configuration

3

ISCR

Input Signal

Conversion Range

1

0

325 mV (282 mV linear range)

98 mV (85 mV linear range)

2

XENMCLKDIV

Enable Master Clock

Division

0

1

MCLK division enabled

MCLK division disabled

1

XOSENABLE

Enable offset

0

1

Offset enabled

Offset disabled

0

OSSELECT

Offset value selection

1

0

+123 mV

+33 mV

MAS6501 has one control register for configuring

the measurement setup. See table 1 for control

register bit definitions. Control register values are

set via I2C bus.

First two OSRS bits of the control register define

four selectable over sampling ratios. The higher

OSR the better ADC accuracy but the longer

conversion time.

The SCO bit controls the A/D conversion. When

SCO = 0, no A/D conversion takes place. When

SCO = 1, the A/D converter turns on and the analog

data is being converted. Then MCLK must be

clocked at least until EOC pin goes high indicating

that conversion has been accomplished.

PTS bit selects between pressure and temperature

measurement. In temperature measurement the

sensor is connected in bridge configuration together

with four integrated resistors (see figure 3 on page 8

and resistors R1, R2, R3 and R4).

ISCR selects between two A/D conversion ranges.

The XENMCLKDIV bit controls the internal clock

frequency of MAS6501, fCLK(INT). When the bit is

low, the MCLK division is enabled and the internal

clock frequency fCLK(INT) = fMCLK/2, where

fMCLK is the master clock frequency. When the

XENMCLKDIV bit is high, the MCLK division is

disabled and fCLK(INT) = fMCLK.

In the XENMCLKDIV = 1 mode the duty cycle

should be as close to 50 % as possible. In this

mode, the conversion time is made half (see page 3

conversion time values with XENMCLKDIV = 1)

compared

to

clock

speed

division

mode

XENMCLKDIV = 0 whereas the resolution remains

unchanged. In XENMCLKDIV = 0 mode the

conversion time and also current consumption are

doubled but then the external master clock signal

MCLK does not need to have close to 50% duty

cycle.

XOSENABLE can be used to enable input signal

range offset option. At 1 value no offset is applied

but at 0 value an offset value which is determined

with OSSELECT bit is used.

OSSELECT selects between two offset values. No

offset

is

applied

if

offset

is

disabled

(XOSENABLE=1).