CPC7594

R03

www.clare.com

19

3.2 Printed-Circuit Board Layout

3.2.1 DFN

NOTE: As the metallic pad on the bottom of the DFN

package is connected to the substrate of the die, Clare

recommends that no printed circuit board traces or

vias be placed under this area to maintain minimum

creepage and clearance values.

3.2.2 SOIC

3.3 Tape and Reel Packaging

3.3.1 DFN

DIMENSIONS

mm

(inches)

5.80

(0.228)

0.35

(0.014)

1.05

(0.041)

0.80

(0.031)

2.00

(0.079)

1.27

(0.050)

mm

(inches)

DIMENSIONS

9.40

(0.370)

0.60

(0.024)

NOTE: Tape dimensions not shown comply with JEDEC Standard EIA-481-2

Dimensions

mm

(inches)

Embossment

Embossed

Carrier

330.2 Dia

(13.00 Dia)

Top Cover

Tape Thickness

0.102 Max

(0.004 Max)

K

(0.063 + 0.004)

B

(0.285 + 0.004)

W=16.00 + 0.30

(0.630 + 0.012)

P=12.00 + 0.10

(0.472 + 0.004)

A

(0.246 + 0.004)

Pin 1

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