AT90SCR100 datasheet(41/433 Pages) ATMEL

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TPR0327AY–SMS–30Jan09

AT90SCR100

• Bits 3..0 – CLKPS3..0 : Clock Prescaler Select Bits 3..0

These bits define the division factor between the selected clock source and the internal system

clock. These bits can be written at run-time to vary the clock frequency to suit the application

requirements. As the divider divides the master clock input to the MCU, the speed of all synchro-

nous peripherals is reduced when a division factor is used. The division factors are given in

Table 7-5.

You can change the CLKPR on the fly. The divider will automatically be active.

Default value of CLKPR is 0x00.

Notes: 1. clkMUX=96Mhz, clock generated by the PLL

2. clkMUX=8Mhz, clock provided by external clock source XTAL.

3. It is impossible for the CPU core to support 96Mhz, thus, by default, the divide by one clock

option generates a 16Mhz clock.

Table 7-5.

Clock Prescaler Select (clkCPU)

CLKPS3

CLKPS2

CLKPS1

CLKPS0

CLKPR

Clock Division

Factor

clk

CPU

(

clk

MUX = clkPLL)

(1)

clk

CPU

(

clk

MUX = clkXTAL)

(2)

000

0x00

1(3)

16Mhz(3)

8Mhz

000

0x01

24Mhz

2Mhz

0x02

19.2Mhz

1.60Mhz

0x03

16Mhz

1.33Mhz

010

0x04

12Mhz

1Mhz

0x05

8Mhz

0.67Mhz

0x06

4Mhz

0.33Mhz

0x07

2Mhz

0.17Mhz

0x08

1Mhz

0.08Mhz

100

0x09

Reserved

101

0x0A

101

0x0B

110

0x0C

110

0x0D

111

0x0E

111

0X0F

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