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AT90SCR100 数据表(PDF) 53 Page - ATMEL Corporation |
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AT90SCR100 数据表(HTML) 53 Page - ATMEL Corporation |
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53 / 433 page  53 TPR0327AY–SMS–30Jan09 AT90SCR100 A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the Power-on Reset threshold voltage invokes the delay counter, which determines how long the device is kept in RESET after VCC rise. The RESET signal is activated again, without any delay, when VCC decreases below the detection level. Figure 9-2. MCU Start-up, RESET Tied to VCC Figure 9-3. MCU Start-up, RESET Extended Externally 9.2.2 External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see Table 9-1) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage – VRST – on its positive edge, the delay counter starts the MCU after the Time-out period – tTOUT – has expired. V RESET TIME-OUT INTERNAL RESET t TOUT V POT V RST CC RESET TIME-OUT INTERNAL RESET t TOUT V POT V RST V CC |
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