ATtiny45 datasheet(79/196 Pages) ATMEL

79 / 196 page

7598H–AVR–07/09

ATtiny25/45/85

13.2

External Clock Source

An external clock source applied to the T0 pin can be used as Timer/Counter clock (clk

T0). The

T0 pin is sampled once every system clock cycle by the pin synchronization logic. The synchro-

nized (sampled) signal is then passed through the edge detector. Figure 13-1 shows a functional

equivalent block diagram of the T0 synchronization and edge detector logic. The registers are

clocked at the positive edge of the internal system clock (clk

I/O). The latch is transparent in the

high period of the internal system clock.

The edge detector generates one clk

T0 pulse for each positive (CSn2:0 = 7) or negative (CSn2:0

= 6) edge it detects.

Figure 13-1. T0 Pin Sampling

The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles

from an edge has been applied to the T0 pin to the counter is updated.

Enabling and disabling of the clock input must be done when T0 has been stable for at least one

system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.

Each half period of the external clock applied must be longer than one system clock cycle to

ensure correct sampling. The external clock must be guaranteed to have less than half the sys-

tem clock frequency (f

ExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses

sampling, the maximum frequency of an external clock it can detect is half the sampling fre-

quency (Nyquist sampling theorem). However, due to variation of the system clock frequency

and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is

recommended that maximum frequency of an external clock source is less than f

clk_I/O/2.5.

An external clock source can not be prescaled.

Tn_sync

(To Clock

Select Logic)

Edge Detector

Synchronization

clk

I/O

ATtiny45 数据表(PDF) 79 Page - ATMEL Corporation

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