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ATtiny45 数据表(PDF) 15 Page - ATMEL Corporation

部件名 ATtiny45
功能描述  8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash
PDF  196 Pages
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制造商  ATMEL [ATMEL Corporation]
网页  http://www.atmel.com
标志 ATMEL - ATMEL Corporation

ATtiny45 数据表(HTML) 15 Page - ATMEL Corporation

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15
7598H–AVR–07/09
ATtiny25/45/85
5.2.1
Data Memory Access Times
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clk
CPU cycles as described in Figure 5-3.
Figure 5-3.
On-chip Data SRAM Access Cycles
5.3
EEPROM Data Memory
The ATtiny25/45/85 contains 128/256/512 bytes of data EEPROM memory. It is organized as a
separate data space, in which single bytes can be read and written. The EEPROM has an
endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the
CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM
Data Register, and the EEPROM Control Register. For a detailed description of Serial data
downloading to the EEPROM, see page 138.
5.3.1
EEPROM Read/Write Access
The EEPROM Access Registers are accessible in the I/O space.
The write access times for the EEPROM are given in Table 5-1. A self-timing function, however,
lets the user software detect when the next byte can be written. If the user code contains instruc-
tions that write the EEPROM, some precautions must be taken. In heavily filtered power
supplies, V
CC is likely to rise or fall slowly on Power-up/down. This causes the device for some
period of time to run at a voltage lower than specified as minimum for the clock frequency used.
See “Preventing EEPROM Corruption” on page 20 for details on how to avoid problems in these
situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
Refer to “Atomic Byte Programming” on page 18 and “Split Byte Programming” on page 18 for
details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.
clk
WR
RD
Data
Data
Address
Address valid
T1
T2
T3
Compute Address
CPU
Memory Access Instruction
Next Instruction



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