LSM320HAY30 datasheet(28/42 Pages) STMICROELECTRONICS

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LSM320HAY30

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Doc ID 16917 Rev 1

The device contains a set of registers which are used to control acceleration portion

behavior and to retrieve acceleration data. The register address, composed of 7 bits, is used

to identify them and to write the data through the serial interface.

8.1

WHO_AM_I (0Fh)

This register is the device identification register, and contains the device identifier which, for

the LSM320HAY30, is set to 32h.

8.2

LA_CTRL_REG1 (20h)

PM bits allow selection between power-down and two operating active modes. The device is

in power-down mode when the PD bits are set to “000” (default value after boot).

Table 18

shows all the possible power mode configurations and respective output data rates. Output

data in the low-power modes are computed with a low-pass filter cut-off frequency defined

by DR1, DR0 bits.

DR bits, in normal mode operation, select the data rate at which acceleration samples are

produced. In low-power mode they define the output data resolution.

Table 19 shows all the

possible configurations for the DR1 and DR0 bits.

Table 15.

WHO_AM_I register

011

Table 16.

LA_CTRL_REG1 register

PM2

PM1

PM0

DR1

DR0

Zen

Yen

Xen

Table 17.

LA_CTRL_REG1 description

PM2 - PM0

Power mode selection. Default value: 000

(000: Power-down; Others: refer to

Table 18)

DR1, DR0

Data rate selection. Default value: 00

(00:50 Hz; others: refer to

Table 19)

Zen

Z axis enable. Default value: 1

(0: Z axis disabled; 1: Z axis enabled)

Yen

Y axis enable. Default value: 1

(0: Y axis disabled; 1: Y axis enabled)

Xen

X axis enable. Default value: 1

(0: X axis disabled; 1: X axis enabled)

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