EVAL-ADE7858EBZ datasheet(41/76 Pages) AD

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Preliminary Technical Data

ADE7858

Rev. PrA | Page 41 of 76



AVAROS



ACCUMULATOR

VARHR[47:0]



32 bit register

AVARHR[31:0]

Output from

Total Reactive Power

Algorithm

ZERO CROSSING

DETECTION

(PHASE B)

ZERO CROSSING

DETECTION

(PHASE C)

ZERO CROSSING

DETECTION

(PHASE A)

ZXSEL[1] in

LCYCMODE[7:0]

ZXSEL[0] in

LCYCMODE[7:0]

ZXSEL[2] in

LCYCMODE[7:0]

CALIBRATION

CONTROL

LINECYC[15:0]

AVARGAIN

Figure 46. ADE7858 Line Cycle Reactive Energy Accumulation Mode

Phase A, Phase B, and Phase C zero crossings are, respectively,

included when counting the number of half-line cycles by

setting bits 5, 4, 3 (ZXSEL) in the LCYCMODE[7:0] register.

Any combination of the zero crossings from all three phases can

be used for counting the zero crossing. Only one phase should

be selected at a time for inclusion in the zero crossings count

during calibration.

For details on setting LINECYC[15:0] register and the interrupt

LENERGY associated with the line cycle accumulation mode,

see Line Cycle Active Energy Accumulation Mode section.

APPARENT POWER CALCULATION

Apparent power is defined as the maximum power that can be

delivered to a load. One way to obtain the apparent power is by

multiplying the voltage rms value by the current rms value:

IRMS

VRMS





(36)

where S is the apparent power and VRMS and IRMS are the rms

voltage and current, respectively. It is also called the arithmetic

apparent power.

The ADE7858 computes the arithmetic apparent power on

each phase. Figure 47 illustrates the signal processing in each

phase for the calculation of the apparent power in the

ADE7858. As VRMS and IRMS contain all harmonic

information, the apparent power computed by the ADE7858 is

a total apparent power.

The ADE7858 stores the instantaneous phase apparent powers

into AVA[23:0], BVA[23:0] and CVA[23:0] registers. Their

expression is:

PMAX

xVA





(37)

where:

x=A, B, C

U, I are the rms values of the phase voltage and current.

UFS, IFS are the rms values of the phase voltage and current when

the ADC inputs are at full scale.

PMAX=33,516,139 is the instantaneous power computed when

the ADC inputs are at full scale and in phase.

The xVA[23:0], x=A, B, C waveform registers may be accessed

using various serial ports. Refer to Waveform Sampling Mode

chapter for more details.

The ADE7858 may compute the apparent power in an

alternative way by multiplying the phase rms current by an rms

voltage introduced externally. See Apparent Power Calculation

using VNOM section for details.



AIRMS

AVAGAIN



ACCUMULATOR

VATHR[47:0]



32 bit register

AVAHR[31:0]

Digital Signal Processor

AVRMS

Figure 47. Apparent Power data flow and Apparent Energy Accumulation

Apparent Power Gain Calibration

The average apparent power result in each phase can be scaled

by ±100% by writing to the phase’s VAGAIN 24-bit register

(AVAGAIN[23:0], BVAGAIN[23:0] or CVAG AIN[23:0]). The

VAGAIN registers are twos complement, signed registers and

have a resolution of 2-23/LSB. The function of the VA gain

registers is expressed mathematically as

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