EVAL-ADE7858EBZ datasheet(50/76 Pages) AD

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ADE7858

Preliminary Technical Data

Rev. PrA| Page 50 of 76

flag, STATUS1[31:0] register has to be written with bit

15(RSTDONE) set to 1.

Certain interrupts are used in conjunction with other status

registers: bits 0 (NLOAD) and 2 (VANLOAD) in MASK1[31:0]

work in conjunction with status bits in PHNOLAD[15:0]. Bits

16, (SAG), 17 (OI) and 18 (OV) in MASK1[31:0] work with

status bits in PHSTATUS[15:0]. Bits 23 (PKI) and 24 (PKV) in

MASK1[31:0] work with status bits in IPEAK[31:0] and

respectively, VPEAK[31:0]. Bits 6, 7, 8 (REVAPx, x=A, B, C), 10,

11, 12 (REVRPx) and 9, 13, 18 (REVPSUMx) in MASK0[31:0]

work with status bits in PHSIGN[15:0]. When STATUSx[31:0]

associated with the bit is immediately read to identify the phase

that triggered the interrupt and only now STATUSx[31:0] is

written back with the bit set to 1.

Using the Interrupts with an MCU

Figure 58 shows a timing diagram that illustrates a suggested

implementation of the ADE7858 interrupt management using

an MCU. At time t1, IRQx pin goes active low indicating that

one or more interrupt events have occurred in the ADE7858.

The IRQx pin should be tied to a negative-edge-triggered

external interrupt on the MCU. On detection of the negative

edge, the MCU should be configured to start executing its

interrupt service routine (ISR). On entering the ISR, all

interrupts should be disabled using the global interrupt mask

bit. At this point, the MCU external interrupt flag can be

cleared to capture interrupt events that occur during the current

ISR. When the MCU interrupt flag is cleared, a read from

STATUSx, the interrupt status register is carried out. The

interrupt status register content is used to determine the source

of the interrupt(s) and hence the appropriate action to be taken.

Then, the same STATUSx content is written back into the

ADE7858 to clear the status flag(s) and reset IRQx line to

logic high (t2). If a subsequent interrupt event occurs during the

ISR (t3) that event is recorded by the MCU external interrupt

flag being set again.

On returning from the ISR, the global interrupt mask bit is

cleared (same instruction cycle) and the external interrupt flag

uses the MCU to jump to its ISR once again. This ensures that

the MCU does not miss any external interrupts.

Figure 59 shows a recommended timing diagram when status

bits in STATUSx registers work in conjunction with bits in

other registers. Same as above, when IRQx pin goes active low,

STATUSx register is read and if one of these bits is 1, then a

second status register is read immediately to identify the phase

that triggered the interrupt. The name PHx in the figure

denotes one of PHSTATUS, IPEAK, VPEAK or PHSIGN

registers. Then STATUSx is written back to clear the status

flag(s).

GLOBAL

INTERRUPT

MASK

JUMP

to ISR

CLEAR MCU

INTERRUPT

FLAG

READ

STATUSx

WRITE

BACK

STATUSx

ISR ACTION

(BASED ON STATUSx CONTENTS)

ISR RETURN

GLOBAL INTERRUPT

MASK RESET

JUMP

to ISR

IRQx

PROGRAM

SEQUENCE

MCU INTERRUPT

FLAG SET

Figure 58. ADE7858 interrupt management

GLOBAL

INTERRUPT

MASK

JUMP

to ISR

CLEAR MCU

INTERRUPT

FLAG

READ

STATUSx

WRITE

BACK

STATUSx

ISR ACTION

(BASED ON STATUSx CONTENTS)

ISR RETURN

GLOBAL INTERRUPT

MASK RESET

JUMP

to ISR

IRQx

PROGRAM

SEQUENCE

MCU INTERRUPT

FLAG SET

READ

PHx

Figure 59. ADE7858 interrupt management when PHSTATUS, IPEAK, VPEAK or PHSIGN registers are involved

SERIAL INTERFACES

The ADE7858 has three serial port interfaces: one fully licensed

I2C interface, one Serial Peripheral Interface (SPI) and one High

Speed Data Capture Port (HSDC). As the SPI pins are

multiplexed with some of the pins of I2C and HSDC ports, the

ADE7858 accepts two configurations: one using SPI port only

and one using I2C port in conjunction with HSDC port.

Serial interface choice

After reset, the HSDC port is always disabled. The choice

between I2C and SPI port is done by manipulating the SS pin

after power up or after a hardware reset. If SS pin is kept high,

then the ADE7858 will use the I2C port until a new hardware

reset is executed. If SS pin is toggled high low 3 times after

power up or after a hardware reset, then the ADE7858 will use

the SPI port until a new hardware reset is executed. This

manipulation of the SS pin can be accomplished in two ways:

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