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EVAL-ADE7858EBZ 数据表(PDF) 57 Page - Analog Devices |
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EVAL-ADE7858EBZ 数据表(HTML) 57 Page - Analog Devices |
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57 / 76 page  Preliminary Technical Data ADE7858 Rev. PrA | Page 57 of 76 REGISTERS LIST Table 21. ADE7858 Registers List located in DSP data memory RAM Address Name R/W1 Bit Length Bit Length during Comm2 Type3 Default Value Description 0x4380 AIGAIN R/W 24 32 ZPSE S 0x000000 Phase A current gain adjust 0x4381 AVGAIN R/W 24 32 ZPSE S 0x000000 Phase A voltage gain adjust 0x4382 BIGAIN R/W 24 32 ZPSE S 0x000000 Phase B current gain adjust 0x4383 BVGAIN R/W 24 32 ZPSE S 0x000000 Phase B voltage gain adjust 0x4384 CIGAIN R/W 24 32 ZPSE S 0x000000 Phase C current gain adjust 0x4385 CVGAIN R/W 24 32 ZPSE S 0x000000 Phase C voltage gain adjust 0x4386 Reserved N/A N/A N/A N/A 0x000000 For proper operation, this memory location should be kept at 0x000000. 0x4387 AIRMSOS R/W 24 32 ZPSE S 0x000000 Phase A current rms offset 0x4388 AVRMSOS R/W 24 32 ZPSE S 0x000000 Phase A voltage rms offset 0x4389 BIRMSOS R/W 24 32 ZPSE S 0x000000 Phase B current rms offset 0x438A BVRMSOS R/W 24 32 ZPSE S 0x000000 Phase B voltage rms offset 0x438B CIRMSOS R/W 24 32 ZPSE S 0x000000 Phase C current rms offset 0x438C CVRMSOS R/W 24 32 ZPSE S 0x000000 Phase C voltage rms offset 0x438D Reserved N/A N/A N/A N/A 0x000000 For proper operation, this memory location should be kept at 0x000000. 0x438E AVAGAIN R/W 24 32 ZPSE S 0x000000 Phase A apparent power gain adjust 0x438F BVAGAIN R/W 24 32 ZPSE S 0x000000 Phase B apparent power gain adjust 0x4390 CVAGAIN R/W 24 32 ZPSE S 0x000000 Phase C apparent power gain adjust 0x4391 AWGAIN R/W 24 32 ZPSE S 0x000000 Phase A total active power gain adjust 0x4392 AWATTOS R/W 24 32 ZPSE S 0x000000 Phase A total active power offset adjust 0x4393 BWGAIN R/W 24 32 ZPSE S 0x000000 Phase B total active power gain adjust 0x4394 BWATTOS R/W 24 32 ZPSE S 0x000000 Phase B total active power offset adjust 0x4395 CWGAIN R/W 24 32 ZPSE S 0x000000 Phase C total active power gain adjust 0x4396 CWATTOS R/W 24 32 ZPSE S 0x000000 Phase C total active power offset adjust 0x4397 AVARGAIN R/W 24 32 ZPSE S 0x000000 Phase A total reactive power gain adjust 0x4398 AVAROS R/W 24 32 ZPSE S 0x000000 Phase A total reactive power offset adjust 0x4399 BVARGAIN R/W 24 32 ZPSE S 0x000000 Phase B total reactive power gain adjust 0x439A BVAROS R/W 24 32 ZPSE S 0x000000 Phase B total reactive power offset adjust 0x439B CVARGAIN R/W 24 32 ZPSE S 0x000000 Phase C total reactive power gain adjust 0x439C CVAROS R/W 24 32 ZPSE S 0x000000 Phase C total reactive power offset adjust 0x439D- 0x43A8 Reserved N/A N/A N/A N/A 0x000000 These memory locations should be kept at 0x000000 for proper operation 0x43A9 VATHR1 R/W 24 32 ZP U 0x000000 Most significant 24 bits of VATHR[47:0] threshold used in phase apparent power data path. 0x43AA VATHR0 R/W 24 32 ZP U 0x000000 Less significant 24 bits of VATHR[47:0] threshold used in phase apparent power data path. 0x43AB WTHR1 R/W 24 32 ZP U 0x000000 Most significant 24 bits of WTHR[47:0] threshold used in phase total/fundamental active power data path. 0x43AC WTHR0 R/W 24 32 ZP U 0x000000 Less significant 24 bits of WTHR[47:0] threshold used in phase total/fundamental active power data path. 0x43AD VARTHR1 R/W 24 32 ZP U 0x000000 Most significant 24 bits of VARTHR[47:0] threshold used in phase total/fundamental reactive power data path. 0x43AE VARTHR0 R/W 24 32 ZP U 0x000000 Less significant 24 bits of VARTHR[47:0] threshold used in phase total/fundamental reactive power data path. 0x43AF reserved N/A N/A N/A N/A 0x000000 This memory location should be kept at 0x000000 for proper operation |
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