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71M6521FE-IM/F 数据表(PDF) 7 Page - Teridian Semiconductor Corporation |
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71M6521FE-IM/F 数据表(HTML) 7 Page - Teridian Semiconductor Corporation |
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7 / 101 page ![]() 71M6521DE/71M6521FE Energy Meter IC DATASHEET JANUARY 2008 v1.0 © 2005-2008 TERIDIAN Semiconductor Corporation Page: 7 of 101 Table 46: Interrupt Enable and Flag Bits.....................................................................................................................33 Table 48: Priority Level Groups....................................................................................................................................34 Table 49: The IP0 Register ..........................................................................................................................................34 Table 50: The IP1 Register: .........................................................................................................................................34 Table 51: Priority Levels...............................................................................................................................................34 Table 52: Interrupt Polling Sequence ...........................................................................................................................35 Table 53: Interrupt Vectors...........................................................................................................................................35 Table 54: Data/Direction Registers and Internal Resources for DIO Pin Groups .........................................................40 Table 55: DIO_DIR Control Bit .....................................................................................................................................40 Table 56: Selectable Controls using the DIO_DIR Bits ................................................................................................41 Table 57: EECTRL Status Bits.....................................................................................................................................42 Table 58: EECTRL bits for 3-wire interface .................................................................................................................43 Table 59: TMUX[4:0] Selections...................................................................................................................................46 Table 60: Available Circuit Functions (“—“ means “not active).....................................................................................50 Table 61: Frequency over Temperature.......................................................................................................................61 Table 62: LCD and DIO Pin Assignment by LCD_NUM for the QFN-68 Package .......................................................64 Table 63: LCD and DIO Pin Assignment by LCD_NUM for the LQFP-64 Package......................................................65 |
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