71M6521FE-IMSLASHF datasheet(14/101 Pages) TERIDIAN

14 / 101 page

71M6521DE/71M6521FE

Energy Meter IC

DATASHEET

JANUARY 2008

Page: 14 of 101

v1.0

Real-Time Monitor

The CE contains a Real-Time Monitor (RTM), which can be programmed through the UART to monitor four selectable CE

DRAM locations at full sample rate. The four monitored locations are serially output to the TMUXOUT pin via the digital output

multiplexer at the beginning of each CE code pass. The RTM can be enabled and disabled with RTM_EN. The RTM output is

clocked by CKTEST. Each RTM word is clocked out in 35 cycles and contains a leading flag bit. See the Functional

Description section for the RTM output format. RTM is low when not in use.

Pulse Generator

The chip contains two pulse generators that create low-jitter pulses at a rate set by either CE or MPU. The function is

distinguished by EXT_PULSE (a CE input variable in CE DRAM):

•

If EXT_PULSE = 1, APULSEW*WRATE and APULSER*WRATE control the pulse rate (external pulse generation)

•

If EXT_PULSE is 0, APULSEW is replaced with WSUM_X and APULSER is replaced with VARSUM_X (internal pulse

generation).

The I/O RAM bits DIO_PV and DIO_PW, as described in the Digital I/O section, can be programmed to route WPULSE to the

output pin DIO6 and VARPULSE to the output pin DIO7. Pulses can also be output on OPT_TX (see OPT_TXE[1:0] for

details).

During each CE code pass, the hardware stores exported sign bits in an 8-bit FIFO and outputs them at a specified interval.

This permits the CE code to calculate all of the pulse generator outputs at the beginning of its code pass and to rely on

hardware to spread them over the MUX frame. The FIFO is reset at the beginning of each MUX frame. PLS_INTERVAL controls

the delay to the first pulse update and the interval between subsequent updates. Its LSB is four CK_FIR cycles, or 4 * 203ns. If

PLS_INTERVAL is zero, the FIFO is deactivated and the pulse outputs are updated immediately.

Thus, NINTERVAL is

4*PLS_INTERVAL.

For use with the standard CE code supplied by TERIDIAN, PLS_INTERVAL is set to a fixed value of 81. PLS_INTERVAL is

specified so that all of the pulse updates are output before the MUX frame completes.

On-chip hardware provides a maximum pulse width feature: PLS_MAXWIDTH[7:0] selects a maximum negative pulse width to

be ‘Nmax’ updates per multiplexer cycle according to the formula: Nmax = (2*PLS_MAXWIDTH+1). If PLS_MAXWIDTH = 255,

no width checking is performed.

Given that PLS_INTERVAL = 81, the maximum pulse width is determined by:

Maximum Pulse Width = (2 * PLS_MAXWIDTH +1) * 81*4*203ns = 65.9µs + PLS_MAXWIDTH * 131.5µs

If the pulse period corresponding to the pulse rate exceeds the desired pulse width, a square wave with 50% duty-cycle is

generated.

The CE pulse output polarity is programmable to be either positive or negative. Pulse polarity may be inverted with PLS_INV.

When this bit is set, the pulses are active high, rather than the more usual active low.

CE Functional Overview

The ADC processes one sample per channel per multiplexer cycle. Figure 4 shows the timing of the samples taken during one

multiplexer cycle.

The number of samples processed during one accumulation cycle is controlled by the I/O RAM registers PRE_SAMPS

(0x2001[7:6]) and SUM_CYCLES (0x2001[5:0]). The integration time for each energy output is

PRE_SAMPS * SUM_CYCLES / 2520.6, where 2520.6 is the sample rate [Hz]

For example, PRE_SAMPS = 42 and SUM_CYCLES = 50 will establish 2100 samples per accumulation cycle. PRE_SAMPS = 100

and SUM_CYCLES = 21 will result in the exact same accumulation cycle of 2100 samples or 833ms. After an accumulation

cycle is completed, the XFER_BUSY interrupt signals to the MPU that accumulated data are available.

71M6521FE-IM/F 数据表(PDF) 14 Page - Teridian Semiconductor Corporation

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