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78M6612-IM/F/P 数据表(PDF) 91 Page - Teridian Semiconductor Corporation |
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78M6612-IM/F/P 数据表(HTML) 91 Page - Teridian Semiconductor Corporation |
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91 / 111 page ![]() DS_6612_001 78M6612 Data Sheet Rev. 1.2 91 5.4 Performance Specifications 5.4.1 Parameter Input Logic Levels Condition Min Typ Max Unit Digital high-level input voltage †, V IH 2 V Digital low-level input voltage †, V IL 0.8 V Input pull-up current, IIL E_RXTX, E_RST, CKTEST Other digital inputs VIN=0V, ICE_E=1 10 10 -1 0 100 100 1 µA µA µA Input pull down current, IIH ICE_E Other digital inputs VIN=V3P3D 10 -1 0 100 1 µA µA † 5.4.2 In battery powered modes, digital inputs should be below 0.3 V or above 2.5 V to minimize battery current. Parameter Output Logic Levels Condition Min Typ Max Unit Digital high-level output voltage V I OH LOAD V3P3D -0.4 = 1 mA V ILOAD V3P3D -0.6 = 15 mA V Digital low-level output voltage V I OL LOAD 0 = 1 mA 0.4 V ILOAD = 15 mA 0.8 V TX1 VOH (V3P3D-TX1) ISOURCE=1 mA 0.4 V TX1 VOL ISINK=20 mA 0.7 V 5.4.3 Parameter Power-Fault Comparator Condition Min Typ Max Unit Offset Voltage V1-VBIAS -20 +15 mV Hysteresis Current V1 Vin = VBIAS – 100 mV 0.8 1.2 µA Response Time V1 +100 mV overdrive 2 5 10 µs W DT Disable Threshold (V1-V3P3A) -400 -10 mV 5.4.4 BME=1 Battery Monitor Parameter Condition Min Typ Max Unit Load Resistor 27 45 63 k Ω LSB Value - FIR_LEN=0 FIR_LEN=1 does not include the 9- bit left shift at CE input. -6.0 -2.6 -5.4 -2.3 -4.9 -2.0 µV µV Offset Error -200 -72 +100 mV |
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