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78M6612-IM/F/P 数据表(PDF) 11 Page - Teridian Semiconductor Corporation |
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78M6612-IM/F/P 数据表(HTML) 11 Page - Teridian Semiconductor Corporation |
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11 / 111 page  DS_6612_001 78M6612 Data Sheet Rev. 1.2 11 rising edge after the last mux state of its sequence, the mux will wait one additional CK32 cycle before beginning a new frame. At the beginning of this cycle, the value of CROSS will be updated according to the CHOP_E bits. The extra CK32 cycle allows time for the chopped VREF to settle. During this cycle, MUXSYNC is held high. The leading edge of muxsync initiates a pass through the CE program sequence. The beginning of the sequence is the serial readout of the four RTM words. CHOP_E 1.2.5 Temperature Sensor has 3 states: positive, reverse, and chop. In the positive state, CROSS is held low. In the reverse state, CROSS is held high. In the chop state, CROSS is toggled near the end of each Mux Frame, as described above. It is desirable that CROSS take on alternate values at the beginning of each Mux cycle. For this reason, if chop state is selected, CROSS will not toggle at the end of the last Mux cycle in a SUM cycle. The internal bias voltage VBIAS (typically 1.6 V) is used by the ADC when measuring the temperature and battery monitor signals. The 78M6612 includes an on-chip temperature sensor implemented as a bandgap reference. It is used to determine the die temperature The MPU may request an alternate multiplexer cycle containing the temperature sensor output by asserting MUX_ALT. The primary use of the temperature data is to determine the magnitude of compensation required to offset the thermal drift in the system (see Section 3.3 Temperature Compensation). 1.2.6 Battery Monitor The battery voltage is measured by the ADC during alternative multiplexer frames if the BME (Battery Measure Enable) bit in the I/O RAM is set. While BME is set, an on-chip 45 k Ω load resistor is applied to the battery, and a scaled fraction of the battery voltage is applied to the ADC input. After each alternative MUX frame, the result of the ADC conversion is available at CE DRAM address 07. BME is ignored and assumed zero when system power is not available (V1 < VBIAS). See Section 5.4.4 Battery Monitor for details regarding the ADC LSB size and the conversion accuracy. 1.2.7 Functional Description The AFE functions as a data acquisition system, controlled by the MPU. The main signals (IA, VA, IB, VB) are sampled and the ADC counts obtained are stored in CE DRAM where they can be accessed by the CE and, if necessary, by the MPU. Alternate multiplexer cycles are initiated less frequently by the MPU to gather access to the slow temperature and battery signals. IA VA MUX VREF 4.9MHz VBIAS CROSS CK32 VREF VREF_DIS MUX CTRL MUX_DIV CHOP_E EQU IB MUX MUX_ALT V3P3A FIR_LEN FIR VB VBIAS VREF_CAL ∆Σ ADC CONVERTER + - VREF ADC_E TEMP VBAT FIR_DONE FIR_START Figure 3: AFE Block Diagram |
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