78M6612-IMSLASHFSLASHP datasheet(13/111 Pages) TERIDIAN

13 / 111 page

DS_6612_001

78M6612 Data Sheet

Rev. 1.2

The CE of the 78M6612 is aided by support hardware that facilitates implementation of equations, pulse

counters, and accumulators. This support hardware is controlled through I/O RAM locations EQU

(equation assist), DIO_PV and DIO_PW (pulse count assist), and PRE_SAMPS and SUM_CYCLES

(accumulation assist). PRE_SAMPS and SUM_CYCLES support a dual level accumulation scheme where

the first accumulator accumulates results from PRE_SAMPS samples and the second accumulator

accumulates up to SUM_CYCLES of the first accumulator results. The integration time for each energy

output is PRE_SAMPS * SUM_CYCLES/2520.6 (with MUX_DIV = 01). CE hardware issues the

XFER_BUSY interrupt when the accumulation is complete.

1.3.1

Measurement Equations

Refer to the applicable 78M6612 Firmware Description Document for further details.

1.3.2

Real-Time Monitor

The CE contains a Real-Time Monitor (RTM), which can be programmed through the UART to monitor

four selectable CE DRAM locations at full sample rate for system debug purposes. The four monitored

locations are serially output to the TMUXOUT pin via the digital output multiplexer at the beginning of

each CE code pass. The RTM can be enabled and disabled with RTM_EN. The RTM output is clocked

by CKTEST. Each RTM word is clocked out in 35 cycles and contains a leading flag bit. See Section 2

Functional Description for the RTM output format. RTM is low when not in use.

1.3.3

Pulse Generator

The chip contains two pulse generators that create low-jitter pulses at a rate set by either CE or MPU for

calibration purposes. The function is distinguished by EXT_PULSE (a CE input variable in CE DRAM):

•

If EXT_PULSE = 1, APULSEW*WRATE and APULSER*WRATE control the pulse rate (external pulse

generation).

•

If EXT_PULSE is 0, APULSEW is replaced with WSUM_X and APULSER is replaced with VARSUM_X

(internal pulse generation).

The I/O RAM bits DIO_PV and DIO_PW, as described in Section 1.5.7 Digital I/O, can be programmed to

route WPULSE to the output pin DIO6 and VARPULSE to the output pin DIO7. Pulses can also be

output on TX1 (see TX1E[1:0] for details).

During each CE code pass, the hardware stores exported sign bits in an 8-bit FIFO and outputs them at

a specified interval. This permits the CE code to calculate all of the pulse generator outputs at the

beginning of its code pass and to rely on hardware to spread them over the MUX frame. The FIFO is

reset at the beginning of each MUX frame. PLS_INTERVAL controls the delay to the first pulse update

and the interval between subsequent updates. Its LSB is four CK_FIR cycles, or 4 * 203ns. If

PLS_INTERVAL is zero, the FIFO is deactivated and the pulse outputs are updated immediately. Thus,

the internal is 4*PLS_INTERVAL.

For use with the standard CE code supplied by Teridian, PLS_INTERVAL is set to a fixed value of 81.

PLS_INTERVAL is specified so that all of the pulse updates are output before the MUX frame completes.

On-chip hardware provides a maximum pulse width feature: PLS_MAXWIDTH[7:0] selects a maximum

negative pulse width to be ‘Nmax’ updates per multiplexer cycle according to the formula: Nmax =

(2*PLS_MAXWIDTH+1). If PLS_MAXWIDTH = 255, no width checking is performed.

Given that PLS_INTERVAL = 81, the maximum pulse width is determined by:

Maximum Pulse Width = (2 * PLS_MAXWIDTH +1) * 81*4*203ns = 65.9µs + PLS_MAXWIDTH *

131.5µs

78M6612-IM/F/P 数据表(PDF) 13 Page - Teridian Semiconductor Corporation

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