PPC5632MF0MMGA4 datasheet(24/118 Pages) FREESCALE

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MPC5634M Microcontroller Data Sheet, Rev. 4

Preliminary—Subject to Change Without Notice

Overview

Freescale Semiconductor

The FlexCAN module provides the following features:

•

Based on and including all existing features of the Freescale TouCAN module

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Full Implementation of the CAN protocol specification, Version 2.0B

— Standard data and remote frames

— Extended data and remote frames

— Zero to eight bytes data length

— Programmable bit rate up to 1 Mbit/s

•

Content-related addressing

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64 / 32 message buffers of zero to eight bytes data length

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Individual Rx Mask Register per message buffer

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Each message buffer configurable as Rx or Tx, all supporting standard and extended messages

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Includes 1088 / 544 bytes of embedded memory for message buffer storage

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Includes a 256-byte and a 128-byte memories for storing individual Rx mask registers

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Full featured Rx FIFO with storage capacity for six frames and internal pointer handling

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Powerful Rx FIFO ID filtering, capable of matching incoming IDs against 8 extended, 16 standard or 32 partial (8 bits)

IDs, with individual masking capability

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Selectable backwards compatibility with previous FlexCAN versions

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Programmable clock source to the CAN Protocol Interface, either system clock or oscillator clock

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Listen only mode capability

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Programmable loop-back mode supporting self-test operation

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3 programmable Mask Registers

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Programmable transmit-first scheme: lowest ID, lowest buffer number or highest priority

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Time Stamp based on 16-bit free-running timer

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Global network time, synchronized by a specific message

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Maskable interrupts

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Warning interrupts when the Rx and Tx Error Counters reach 96

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Independent of the transmission medium (an external transceiver is assumed)

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Multi master concept

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High immunity to EMI

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Short latency time due to an arbitration scheme for high-priority messages

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Low power mode, with programmable wake-up on bus activity

1.3.18

System timers

The system timers provide two distinct types of system timer:

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Periodic interrupts/triggers using the Peripheral Interrupt Timer (PIT)

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Operating system task monitors using the System Timer Module (STM)

1.3.18.1

Peripheral Interrupt Timer (PIT)

The PIT provides five independent timer channels, capable of producing periodic interrupts and periodic triggers. The PIT has

no external input or output pins and is intended to be used to provide system ‘tick’ signals to the operating system, as well as

periodic triggers for eQADC queues. Of the five channels in the PIT, four are clocked by the system clock, one is clocked by

the crystal clock. This one channel is also referred to as Real Time Interrupt (RTI) and is used to wakeup the device from low

power stop mode.

The following features are implemented in the PIT:

PPC5632MF0MMGA4 数据表(PDF) 24 Page - Freescale Semiconductor, Inc

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