AD9992BBCZ datasheet(16/92 Pages) AD

16 / 92 page

AD9992

Rev. C | Page 16 of 92

H-Driver and RG Outputs

In addition to the programmable timing positions, the AD9992

features on-chip output drivers for the RG, HL, and H1 to H8

outputs. These drivers are powerful enough to drive the CCD

inputs directly. The H-driver and RG current can be adjusted

for optimum rise/fall time for a particular load by using the drive

strength control registers (Address 0x35 and Address 0x36).

The 3-bit drive setting for each output is adjustable in 4.3 mA

increments: 0 = three-state; 1 = 4.3 mA; 2 = 8.6 mA; 3 = 12.9 mA;

and 4, 5, 6, 7 = 17.2 mA.

As shown in Figure 16, when HCLK Mode 1 is used, the H2,

H4, H6, and H8 outputs are inverses of the H1, H3, H5, and H7

outputs, respectively. Using the HCLKMODE register (Address

0x23, Bits [9:7]), it is possible to select a different configuration.

Table 9 shows a comparison of the different programmable

settings for each HCLK mode. Figure 17 and Figure 18 show

the settings for HCLK Mode 2 and HCLK Mode 3, respectively.

It is recommended that all H1 to H8 outputs on the AD9992

be used together for maximum flexibility in drive strength

settings. A typical CCD with H1 and H2 inputs should only

have the AD9992 H1, H3, H5, and H7 outputs connected

together to drive the CCD’s H1, and the H2, H4, H6, and H8

outputs connected together to drive the CCD’s H2. Similarly,

a CCD with H1, H2, H3, and H4 inputs should have

•

H1 and H3 connected to the CCD’s H1.

•

H2 and H4 connected to the CCD’s H2.

•

H5 and H7 connected to the CCD’s H3.

•

H6 and H8 connected to the CCD’s H4.

Table 8. Timing Core Register Parameters for H1, H2, HL, RG, SHP, SHD

Parameter

Length

Range

Description

Polarity

High/low

Polarity control for H1, H2, HL, and RG (0 = inversion, 1 = no inversion)

Positive Edge

0 to 63 edge location

Positive edge location for H1, H2, HL, and RG

Negative Edge

0 to 63 edge location

Negative edge location for H1, H2, HL, and RG

Sampling Location

0 to 63 edge location

Sampling location for internal SHP and SHD signals

Drive Strength

0 to 4 current steps

Drive current for H1 to H8 , HL, and RG outputs (4.3 mA per step)

Table 9. HCLK Modes, Selected by Address 0x23, Bits[9:7]

HCLKMODE

Description

Mode 1

001

H1 edges are programmable, with H3 = H5 = H7 = H1, H2 = H4 = H6 = H8 = inverse of H1

Mode 2

010

H1 edges are programmable, with H3 = H5 = H7 = H1

H2 edges are programmable, with H4 = H6 = H8 = H2

Mode 3

100

H1 edges are programmable, with H3 = H1 and H2 = H4 = inverse of H1

H5 edges are programmable, with H7 = H5 and H6 = H8 = inverse of H5

Invalid Selection

000, 011, 101, 110, 111

Invalid register settings

H1 TO H8 PROGRAMMABLE LOCATIONS:

1H1 RISING EDGE.

2H1 FALLING EDGE.

3H2 RISING EDGE.

4H2 FALLING EDGE.

H2, H4, H6, H8

H1, H3, H5, H7

Figure 17. HCLK Mode 2 Operation

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