AD9992BBCZ datasheet(24/92 Pages) AD

24 / 92 page

AD9992

Rev. C | Page 24 of 92

HBLK

H-CLOCK FREQUENCY CAN BE REDUCED DURING HBLK BY 1/2 (AS SHOWN),

1/4, 1/6, 1/8, 1/10, 1/12, AND SO ON, UP TO 1/30 USING HBLKWIDTH REGISTER

H1/H3

H2/H4

1/FPIX

2 × (1/FPIX)

Figure 28. Generating Wide H-Clock Pulses During HBLK Interval

HBLKSTART

HBLKEND

REPEAT AREA 0

REPEAT AREA 1 REPEAT AREA 2 REPEAT AREA 3

REPEAT AREA 4 REPEAT AREA 5

MASK A, B, C PULSES IN ANY REPEAT

AREA BY SETTING RA*H*REP* = 0

CHANGE NUMBER OF A, B, C PULSES IN ANY

REPEAT AREA USING RA*H*REP* REGISTERS

CREATE UP TO 3 GROUPS OF TOGGLES

A, B, C COMMON IN ALL REPEAT AREAS

Figure 29. HBLK Mode 2 Operation

HBLK

HBLKSTART

HBLKSTARTA

HBLKEND

HBLKLEN

REPEAT AREA 0

HBLKREP = 2

TO CREATE TWO REPEAT AREAS

REPEAT AREA 1

HBLKSTARTB

HBLKSTARTC

RA0H1REPA RA0H1REPB

RA0H1REPC

ALL RA*H*REPA/B/C REGISTERS = 2 TO CREATE TWO HCLK PULSES

RA1H1REPA RA1H1REPB

RA1H1REPC

RA0H2REPA RA0H2REPB

RA0H2REPC

RA1H2REPA RA1H2REPB

RA1H2REPC

Figure 30. HBLK Mode 2 Registers

AD9992BBCZ 数据表(PDF) 24 Page - Analog Devices

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