AD9992BBCZ datasheet(3/92 Pages) AD

3 / 92 page

AD9992

Rev. C | Page 3 of 92

SPECIFICATIONS

Table 1.

Parameter

Min

Typ

Max

Unit

TEMPERATURE RANGE

Operating

−25

+85

°C

Storage

−65

+150

°C

POWER SUPPLY VOLTAGE INPUTS

AVDD (AFE Analog Supply)

1.6

1.8

2.0

TCVDD (Timing Core Supply)

1.6

1.8

2.0

CLIVDD (CLI Input Supply)

1.6

3.0

3.6

RGVDD (RG, HL Driver)

2.7

3.0

3.6

HVDD1/HVDD2 (H1 to H8 Drivers)1

2.7

3.0

3.6

DVDD (Digital Logic)

1.6

1.8

2.0

DRVDD (Parallel Data Output Drivers)

1.6

3.0

3.6

IOVDD (Digital I/O)

1.6

3.0

3.6

XVVDD (Vertical Output Drivers)

1.6

3.0

3.6

CP1P8 (CP Supply Input)

1.6

1.8

2.0

LDOIN (LDO Supply Input)

2.25

3.0

3.6

POWER SUPPLY CURRENTS—40 MHz OPERATION

AVDD (1.8 V)

TCVDD (1.8 V)

CLIVDD (3 V)

1.5

RGVDD (3.3 V, 20 pF RG Load, 20 pF HL Load)

HVDD1/HVDD2 (3.3 V, 480 pF Total Load on H1 to H8)1

DVDD (1.8 V)

9.5

DRVDD (3 V, 10 pF Load on Each DOUT Pin)

IOVDD (3 V, Depends on Load and Output Frequency of Digital I/O)

XVVDD (3 V, Depends on Load and Output Frequency of XV Signals)

POWER SUPPLY CURRENTS—STANDBY MODE OPERATION

Standby1 Mode

Standby2 Mode

Standby3 Mode

1.5

MAXIMUM CLOCK RATE (CLI)

MHz

1 The total power dissipated by the HVDD (or RGVDD) supply can be approximated using the equation

Total HVDD Power = [CL × HVDD × Pixel Frequency] × HVDD

Reducing the capacitive load and/or reducing the HVDD supply reduces the power dissipation. CL is the total capacitance seen by all H-outputs.

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