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Revision 1.02

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AS1524/AS1525

Datasheet - A p p l i c a t i o n I n f o r m a t i o n

Figure 27. QSPI Serial Interface Timing (CPOL = CPHA = 0)

PIC16 and SSP Module and PIC17 Interface

The AS1524/AS1525 are compatible with a PIC16/PIC17 controllers, using the synchronous serial port (SSP) module

To establish SPI communication, connect the PIC16/PIC17 controllers as shown in Figure 28 and configure the PIC16/

PIC17 as system master. This is done by initializing its synchronous serial port control register (SSPCON) and syn-

chronous serial port status register (SSPSTAT) to the bit patterns shown in Table 6 on page 18 and Table 7 on

page 18.

Figure 28. SPI Interface Connections for PIC16/PIC17 Controller

In SPI mode, the PIC16/PIC17 processor allow 8 bits of data to be synchronously transmitted and received simultane-

ously. Two consecutive 8-bit readings (see Figure 29) are necessary to obtain the entire 12-bit result from the AS1524/

AS1525. DOUT data transitions on the serial clock’s falling edge and is clocked into the processor on SCLK’s rising

edge.

The first 8-bit data stream contains the first 8 data bits starting with the MSB. The second data stream contains the

remaining bits, D3 through D0.

Figure 29. SPI Interface Timing with PIC16/PIC17 in Master Mode (CKE = 1. CKP = 0. SMP = 0, SSPM3:SSPM0

= 0001)

SCLK

CNVST

Sampling Instant

1

4

8

12

DOUT

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B11

MSB

B0

LSB

High Z

16

AS1524/

AS1525

PIC16/

PIC17

DOUT

CNVST

SCLK

7

DOUT

6

CNVST

8

SCLK

SCLK

CNVST

Sampling Instant

1

4

8

12

DOUT

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B11

MSB

B0

LSB

High Z

16

1st Byte Read

2nd Byte Read