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Revision 1.02

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AS1524/AS1525

Datasheet - A p p l i c a t i o n I n f o r m a t i o n

Table 6. SSPCON Register Settings

Control Bit

AS1524/AS1525

Setting

Synchronous Serial Port Control Register (SSPCON)

WCOL

Bit 7

X

Write Collision Detection Bit

SSPOV

Bit 6

X

Receive Overflow Detect Bit

SSPEN

Bit 5

1

Synchronous Serial Port Enable

0: Disables serial port and configures these pins as I/O port pins.

1: Enables serial port and configures SCK, SDO, and SCI pins as serial port

pins.

CKP

Bit 4

0

Clock Polarity Select Bit. CKP = 0 for SPI master mode selection.

SSPM3:1

Bit 3:1

0

Synchronous Serial Port Mode Select Bit. Sets SPI master mode and

selects FCLK = fOSC / 16.

SSPM0

Bit 0

1

Table 7. SSPSTAT Register Settings

Control Bit

AS1524/AS1525

Setting

Synchronous Serial Status Register (SSPSTAT)

SMP

Bit 7

0

SPI Data Input Sample Phase. Input data is sampled at the middle of the

data output time.

CKE

Bit 6

1

SPI Clock Edge Select Bit. Data is transmitted on the rising edge of the

serial clock.

D/A

Bit 5

X

Data Address Bit

PBit 4

X

Stop Bit

SBit 3

X

Start Bit

R/W

Bit 2

X

Read/Write Bit Information

UA

Bit 1

X

Update Address

BF

Bit 0

X

Buffer Full Status Bit