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Revision 1.01

8 - 22

AS1536/AS1537

Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s

Timing Characteristics

Figure 3. DOUT Enable-Time Load Circuits

Figure 4. DOUT Disable-Time Load Circuits

Table 4. Timing Characteristics

Parameter

Symbol

Conditions

Min

Typ

Max

Units

Acquisition Time

1

minimum time needed for the signal to be acquired

1.5

µs

SCLK Falling-to-DOUT Valid

20

200

ns

CSN Falling-to-Output Enable

240

ns

CSN Rising-to-Output Disable

240

ns

SCLK Clock Frequency

0

2.1

MHz

SCLK Pulse Width High

200

ns

SCLK Pulse Width Low

200

ns

SCLK Low-to-CSN Falling Setup

Time

50

ns

DOUT Rising-to-SCLK Rising

2

2. Guaranteed by design; not subject to production testing.

0

ns

CSN Pulse Width

240

ns

50pF

50pF

6k

Ω

GND

DGND

DOUT

DOUT

+2.7V

6k

Ω

DGND

6k

Ω

50pF

50pF

6k

Ω

DGND

GND

DGND

DOUT

DOUT

+2.7V