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AS1536 数据表(PDF) 6 Page - ams AG |
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AS1536 数据表(HTML) 6 Page - ams AG |
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6 / 21 page ![]() www.austriamicrosystems.com Revision 1.01 7 - 22 AS1536/AS1537 Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s Digital Inputs: SCLK, SHDNN, CSN VIH SCLK, CSN Input High Voltage 0.7x VDD V VIL SCLK, CSN Input Low Voltage 0.3x VDD V VHYST SCLK, CSN Input Hysteresis 0.2 V IIN SCLK, CSN Input Leakage VIN = 0V or VDD ±0.01 ±1 µA CIN SCLK, CSN Input Capacitance 7 15 pF VSH SHDNN Input High Voltage VDD - 0.4 V VSL SHDNN Input Low Voltage 0.4 V SHDNN Input Current SHDNN = 0V or VDD ±4.0 µA VSM SHDNN Input Mid Voltage 1.1 VDD - 1.1 V VFLT SHDNN Voltage, Floating SHDNN = float VDD/2 V SHDNN Max Allowed Leakage, Mid Input SHDNN = float ±50 nA Digital Output: DOUT VOL Output Voltage Low ISINK = 5mA 0.4 V ISINK = 16mA 0.8 VOH Output Voltage High ISOURCE = 0.5mA VDD - 0.5 V IL Tri-State Leakage Current CSN = VDD ±0.01 ±10 µA COUT Tri-State Output Capacitance CSN = VDD 7 15 pF Power Requirements VDD Supply Voltage 2.7 5.25 V IDD Supply Current Int. Reference (AS1536), VDD = 3.6V 1.4 2.0 mA Int. Reference (AS1536), VDD = 5.25V 1.6 2.3 External Reference, VDD = 3.6V 1.0 1.4 External Reference, VDD = 5.25V 1.2 1.7 Shutdown mode, VDD = 3.6V 0.3 2 µA Shutdown mode, VDD = 5.25V 0.6 4 PSR Power-Supply Rejection 8 VDD = VDDMIN to VDDMAX, full-scale input ±1 mV 1. Tested at VDD = +2.7V. 2. Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and offset have been calibrated. 3. Offset nulled. 4. Achievable with standard timing (see Figure 25 on page 14). 5. Sample tested at 0.1% AQL. 6. External load should not change during conversion for specified accuracy. 7. Guaranteed by design; not subject to production testing. 8. Measured as [VFS(VDDMIN) - VFS(VDDMAX)] with external reference. Table 3. Electrical Characteristics (Continued) Symbol Parameter Conditions Min Typ Max Units |
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