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Revision 1.01

20 - 22

AS1536/AS1537

Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g s

10 Package Drawings and Markings

Figure 38. 8-pin SOIC-150 Package

Symbol

Min

Max

A1

0.10

0.25

B

0.36

0.46

C

0.19

0.25

D

4.80

4.98

E

3.81

3.99

e1.27BSC

H

5.80

6.20

h

0.25

0.50

L

.041

1.27

A

1.52

1.72

0º

8º

ZD

0.53REF

A2

1.37

1.57

Notes:

1. Lead coplanarity should be 0 to 0.10mm (.004”) max.

2. Package surface finishing:

(2.1) Top: matte (charmilles #18-30).

(2.2) All sides: matte (charmilles #18-30).

(2.3) Bottom: smooth or matte (charmilles #18-30).

3. All dimensions exclusive of mold flash, and end flash from the pack-

age body shall not exceed 0.24mm (0.10”) per side (D).

4. Details of pin #1 identifier are optional but must be located within

the zone indicated.