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DM6580E 数据表(PDF) 40 Page - Davicom Semiconductor, Inc. |
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DM6580E 数据表(HTML) 40 Page - Davicom Semiconductor, Inc. |
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40 / 48 page ![]() DM562P V.90 Integrated Data/ Fax/Voice/Speakerphone Modem Device Single Chip with Memory Built in 40 Final Chip 2 : DM6580 Analog Front End DM6580 Description The DM6580 is a single chip Analog Front End (AFE) designed to be implemented in voice grade modems for data rates up to 56000bps. The DM6580 is an essential part the complete modem device set. The AFE converts the analog signal into digital form and transfers the digital data to the DSP through the serial port. All the clock information needed in a modem device is also generated in the DM6580. Differential analog outputs are provided to achieve the maximum output signal level. An audio monitor with programmable volume levels is built in to monitor the on-line signal. Inside the device, a 16-bit ADC and a 16-bit DAC with over-sampling and noise-shaping techniques is implemented to maximize performance. The DM6580 offers wide-band transmit and receive filters so that the voice band signal is transmitted or received without amplitude distortion and with minimum group delay. In order to support multi-mode modem standards, such as V.90, V.34+, V.32bis, V.32, V.22bis, V.22, V.23, V.21, Bell 212A, Bell 103, V.17, V.29, V.27ter, programmable baud and data rate clock generators are provided. For asymmetric channel usage, the transmit and receive clock generators are independent. In order to enhance echo-cancellation, the receive clock is synchronized with the transmit clock and the best receive timing sample is reconstructed by a reconstruction filter. The Transmit Digital Phase Lock Loop (DPLL) is self-tuning to provide a master, slave or free-running mode for the data terminal interface. A receive DPLL that is step programmable by the host DSP is implemented to get the best samples for the relevant signal processing. DM6580 Block Diagram RxSCLK RxDCLK RFS DOR DIR TFS DOT DIT Digital Reconstruction Filter SCLK Digital Interface Rx Clock System Tx Clock System Divider Control Registers Tx Filter & DAC Rx Filter & ADC LPF & Attenuator Voltage Reference 0/-6 dB Audio Amplifier Power-on Detector SPKR RxIN VREFN VREFP TxA2 TxA1 CLKIN TxSCLK*2 TxDCLK ExtCLK VCM Version: DM562P-DS-F01 February 02, 2004 |
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