AD5174BCPZ-10-R2 datasheet(4/20 Pages) AD

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AD5174

Rev. 0 | Page 4 of 20

Parameter

Symbol

Test Conditions/Comments

Min

Typ1

Max

Unit

DYNAMIC CHARACTERISTICS4, 10

Bandwidth

−3 dB, RAW = 5 kΩ, Terminal W, see Figure 24

700

kHz

Total Harmonic Distortion

VA = 1 V rms, f = 1 kHz, RAW = 5 kΩ

−90

Resistor Noise Density

RWB = 5 kΩ, TA = 25°C, f = 10 kHz

nV/√Hz

1 Typical specifications represent average readings at 25°C, VDD = 5 V, and VSS = 0 V.

2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from the ideal between successive tap positions.

3 The maximum current in each code is defined by IAW = (VDD − 1)/RAW.

4 Guaranteed by design and not subject to production test.

5 See Figure 9 for more details.

6 Resistor Terminal A and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground referenced bipolar

signal adjustment.

7 Different from operating current; the supply current for the fuse program lasts approximately 55 ms.

8 Different from operating current; the supply current for the fuse read lasts approximately 500 ns.

9 PDISS is calculated from (IDD × VDD) + (ISS × VSS).

10 All dynamic characteristics use VDD = +2.5 V, VSS = −2.5 V.

INTERFACE TIMING SPECIFICATIONS

VDD = 2.7 V to 5.5 V, VSS = 0 V; VDD = 2.5 V, VSS = −2.5 V; all specifications TMIN to TMAX, unless otherwise noted.

Table 2.

Parameter

Limit1

Unit

Test Conditions/Comments

t12

ns min

SCLK cycle time

ns min

SCLK high time

ns min

SCLK low time

ns min

SYNC to SCLK falling edge setup time

ns min

Data setup time

ns min

Data hold time

ns min

SCLK falling edge to SYNC rising edge

t83

400

ns min

Minimum SYNC high time

ns min

SYNC rising edge to next SCLK fall ignored

t104

450

ns max

SCLK rising edge to SDO valid

tMEMORY_READ

μs max

Memory readback execute time

tMEMORY_PROGRAM

350

ms max

Memory program time

tRESET

600

μs max

Reset OTP restore time

tPOWER-UP5

ms max

Power-on 50-TP restore time

1 All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

2 Maximum SCLK frequency is 50 MHz.

3 Refer to t

MEMORY_READ

and tMEMORY_PROGRAM for memory commands operations.

4 RPULL_UP = 2.2 kΩ to VDD with a capacitance load of 168 pF.

5 Maximum time after VDD − VSS is equal to 2.5 V.

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