| 数据搜索系统,热门电子元器件搜索 |
|
AD5174BCPZ-10-R2 数据表(PDF) 12 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
AD5174BCPZ-10-R2 数据表(HTML) 12 Page - Analog Devices |
|
12 / 20 page ![]() AD5174 Rev. 0 | Page 12 of 20 THEORY OF OPERATION The AD5174 is designed to operate as a true variable resistor for analog signals within the terminal voltage range of VSS < VTERM < VDD. The RDAC register contents determine the resistor wiper position. The RDAC register acts as a scratchpad register, which allows unlimited changes of resistance settings. The RDAC register can be programmed with any position setting by using the SPI interface. When a desirable wiper position is found, this value can be stored in a 50-TP memory register. Thereafter, the wiper position is always restored to that position for subsequent power-ups. The storing of 50-TP data takes approximately 350 ms; during this time, the AD5174 locks to prevent any changes from taking place. The AD5174 also feature a patented 1% end-to-end resistor tolerance. This simplifies precision, rheostat mode, and open- loop applications where knowledge of absolute resistance is critical. SERIAL DATA INTERFACE The AD5174 contains a serial interface (SYNC, SCLK, DIN, and SDO) that is compatible with SPI interface standards, as well as most DSPs. This device allows writing of data via the serial interface to every register. SHIFT REGISTER The shift register is 16 bits wide, as shown in Figure 2. The 16-bit word consists of two unused bits, which should be set to 0, followed by four control bits and 10 RDAC data bits. Data is loaded MSB first (Bit D9). The four control bits determine the function of the software command as listed in Table 6. Figure 3 shows a timing diagram of a typical AD5174 write sequence. The write sequence begins by bringing the SYNC line low. The SYNC pin must be held low until the complete data-word is loaded from the DIN pin. When SYNC returns high, the serial data-word is decoded according to the instructions in . The command bits (Cx) control the operation of the digital potentiometer. The data bits (Dx) are the values that are loaded into the decoded register. The AD5174 has an internal counter that counts a multiple of 16 bits (a frame) for proper operation. For example, AD5174 works with a 32-bit word but does not work properly with a 31-bit or 33-bit word. The AD5174 does not require a continuous SCLK when Table 6 SYNC is high. To minimize power consumption in the digital input buffers, operate all serial interface pins close to the VDD supply rails. RDAC REGISTER The RDAC register directly controls the position of the digital rheostat wiper. For example, when the RDAC register is loaded with all 0s, the wiper is connected to Terminal A of the variable resistor. The RDAC register is a standard logic register, and there is no restriction on the number of changes allowed. The basic mode of setting the variable resistor wiper position (programming the RDAC register) is accomplished by loading the serial data input register with Command 1 (see Table 6) and with the desired wiper position data. 50-TP MEMORY BLOCK The AD5174 contains an array of 50-TP programmable memory registers, which allow the wiper position to be programmed up to 50 times. Table 10 shows the memory map. When the desired wiper position is determined, the user can load the serial data input register with Command 3 (see Table 6), which stores the wiper position data in a 50-TP memory register. The first address to be programmed is Location 0x01 (see Table 10); the AD5174 increments the 50-TP memory address for each subsequent program until the memory is full. Programming data to 50-TP consumes approximately 4 mA for 55 ms, and takes approx- imately 350 ms to complete, during which time the shift register locks to prevent any changes from occurring. Bit C2 of the control register can be polled to verify that the fuse program command was completed properly. No change in supply voltage is required to program the 50-TP memory; however, a 1 μF capacitor on the EXT_CAP pin is required (see Figure 28). Prior to 50-TP activation, the AD5174 presets to midscale on power-up. WRITE PROTECTION At power-up, the serial data input register write commands for both the RDAC register and the 50-TP memory registers are disabled. The RDAC write protect bit, C1, of the control register (see Table 8 and Table 9) is set to 0 by default. This disables any change of the RDAC register content regardless of the software commands, except that the RDAC register can be refreshed from the 50-TP memory using the software reset, Command 4 (see Table 6). To enable programming of the RDAC register, the write protect bit (Bit C1), of the control register must first be programmed by loading the serial data input register with Command 7. To enable programming of the 50-TP memory, the program enable bit (Bit C0) of the control register, which is set to 0 by default, must first be set to 1. |
|
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |