AD5174

Rev. 0 | Page 7 of 20

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

SYNC

2

A

10

9 SCLK

3

W

4

SDO

8

7

5

EXT_CAP

DIN

6 GND

AD5174

A

W

SDO

10

9

8

SCLK

7

5

EXT_CAP

DIN

6

GND

AD5174

TOP VIEW

(Not to Scale)

SYNC

(EXPOSED

PAD)*

Figure 5. MSOP Pin Configuration

Figure 6. LFCSP Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

Positive Power Supply. Decouple this pin with 0.1 μF ceramic capacitors and 10 μF capacitors.

2

A

3

W

4

Negative Supply. Connect to 0 V for single-supply applications. Decouple this pin with 0.1 μF ceramic capacitors

and 10 μF capacitors.

5

EXT_CAP

rating of ≥7 V.

6

GND

Ground Pin, Logic Ground Reference.

7

SDO

Serial Data Output. This open-drain output requires an external pull-up resistor. SDO can be used to clock data

from the shift register in daisy-chain mode or in readback mode.

8

DIN

Serial Data Line. This pin is used in conjunction with the SCLK line to clock data into or out of the 16-bit

input register.

9

SCLK

Serial Clock Input. Data is clocked into the shift register on the falling edge of the serial clock input. Data can be

transferred at rates of up to 50 MHz.

10

SYNC

Falling Edge Synchronization Signal. This is the frame synchronization signal for the input data. When SYNC

goes low, it enables the shift register and data is transferred in on the falling edges of the subsequent clocks.

by the RDAC.

EPAD

Exposed Pad