ADL5801

Rev. 0 | Page 11 of 20

CIRCUIT DESCRIPTION

The ADL5801 includes a double-balanced active mixer with a

50 Ω input impedance and 250 Ω output impedance. In addition,

the ADL5801 integrates a local oscillator (LO) amplifier and

an RF power detector that can be used to optimize the mixer

dynamic range. The RF and LO are differential, providing max-

imum usable bandwidth at the input and output ports. The LO

also operates with a 50 Ω input impedance and can, optionally,

be operated differentially or single ended. The input, output, and

LO ports can be operated over an exceptionally wide frequency

range. The ADL5801 can be configured as a downconvert mixer

or as an upconvert mixer.

The ADL5801 can be divided into the following sections: the

LO amplifier and splitter, the RF voltage-to-current (V-to-I)

converter, the mixer core, the output loads, the RF detector, and

the bias circuit. A simplified block diagram of the device is

shown in Figure 27. The LO block generates a pair of

differential LO signals to drive two mixer cores. The RF input

power is converted into RF currents by the V-to-I converter that

then feed into the two-mixer core. The internal differential load

of the mixer provides a wideband 250 Ω output impedance from

the mixer. Reference currents to each section are generated by

the bias circuit, which can be enabled or disabled using the ENBL

pin. A detailed description of each section of the ADL5801

follows.

GND

VPLO

ENBL VSET

VPDT

GND

RFIP

NC

GND

VPLO

7

8

15

16

17

18

21

22

23

ADL5801

19

20

GND

IFON

13

14

DETO GND

VPRF

GND

GND

GND

IFOP

RFIN

GND

GND

LOIP

LOIN

6

5

4

3

2

1

24

9

10

11

12

DET

V2I

Figure 27. Block Diagram

LO AMPLIFIER AND SPLITTER

The LO input is conditioned by a series of amplifiers to provide

a well controlled and limited LO swing to the mixer core, result-

ing in excellent input IP3. The LO input is amplified using a

broadband low noise amplifier (LNA) and is then followed by

LO limiting amplifiers. The LNA input impedance is nominally

50 Ω. The LO circuit exhibits low additive noise, resulting in an

excellent mixer noise figure and output noise under RF

blocking. For optimal performance, the LO inputs should be

driven differentially but at lower frequencies; single-ended drive

is acceptable.

RF VOLTAGE-TO-CURRENT (V-TO-I) CONVERTER

The differential RF input signal is applied to a V-to-I converter

that converts the differential input voltage to output currents.

The V-to-I converter provides a 50 Ω input impedance.The V-to-

I section bias current can be adjusted up or down using the

VSET pin. Adjusting the current up improves IP3 and P1dB

input but degrades the SSB noise figure. Adjusting the current

down improves the SSB noise figure but degrades IP3 and P1dB

input. Conversion gain remains nearly constant over a wide

range of VSET pin settings, allowing the part to be adjusted

dynamically without affecting conversion gain. The current

adjustment can be made by connecting a resistor from the

VSET pin to the positive supply to increase the bias current or

from the VSET pin to ground to decrease the bias current.

Optionally, the VSET pin can be connected to the DETO pin to

provide automatic setting of the mixer core current.

MIXER CORE

The ADL5801 has a double-balanced mixer that uses high per-

formance SiGe NPN transistors. This mixer is based on the

Gilbert cell design of four cross-connected transistors.

MIXER OUTPUT LOAD

The mixer load uses a pair of 125 Ω resistors connected to the

positive supply. This provides a 250 Ω differential output resis-

tance. The mixer output should be pulled to the positive supply

externally using a pair of RF chokes or using an output trans-

former with the center tap connected to the positive supply. It

is possible to exclude these components when the mixer core

current is low, but both P1dB input and IP3 input are then

reduced.

The mixer load output can operate from direct current (dc) up

to approximately 600 MHz into a 200 Ω load. For upconversion

applications, the mixer load can be matched using off-chip

matching components. Transmit operation up to 2 GHz is

possible. See the Applications Information section for matching

circuit details.

RF DETECTOR

An RF power detector is buffered from the V-to-I converter

section. This detector has a power response range from

approximately −25 dBm up to 0 dBm and provides a current

output. The output current is designed to be connected to the

VSET pin to boost the mixer core current when large RF signals

are present at the mixer input. An external capacitor can be

used to adjust the response time of this function. If not used,

the DETO pin can be left open or connected to ground.