WM2331IDTSLASHV datasheet(7/25 Pages) WOLFSON

7 / 25 page

Production Data

WM2331

WOLFSON MICROELECTRONICS LTD

PD Rev 1.4 April 2001

Output

hi - Z

Input

hi - Z

Output

OEB

tDZ

OEW

tWRP

tWOE

tDH

tDS

tDEN

DIO[9:0]

Note: All timing measurements are based on 50% of edge transition

Figure 1 Write Timing

Sample 1

Sample 5

Sample 4

Sample 3

Sample 2

tCLK

tCL

tCH

Digital Output

Pipeline Delay

Sample 1

Sample 2

Note: All timing measurements are based on 50% of edge transition

CLK

Analogue Input

at AIN

Figure 2 Output Timing

Test Conditions:

AVDD = DVDD = 3.0V, fCLK = 30MHz, 50% duty cycle, MODE = AVDD, REFTS = 2.5V, REFBS = 0.5V, PGA gain = 1.0,

TA = TMIN to TMAX, unless otherwise stated.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Clock

Clock period

tCLK

Clock high time

tCH

16.5

Clock low time

tCL

16.5

Timing

Pipeline delay

CLK cycles

Clock to data valid

Output disable to hi-Z output

tDZ

020

Output enable to data valid

tDEN

020

Output disable to write enable

tOEW

Write disable to output enable

tWOE

Write pulse width

tWRP

Input data setup time

tDS

5ns

Input data hold time

tDH

5ns

WM2331IDT/V 数据表(PDF) 7 Page - Wolfson Microelectronics plc

WM2331IDT/V 数据表(HTML) 7 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

数据表下载