Production Data

WM2613

WOLFSON MICROELECTRONICS LTD

Production Data Rev 1.0 June 1999

9

PARALLEL INTERFACE

The device latches data on the positive edge of NWE. It must be enabled with NCS low. Whether the

data is written to one of the DAC holding latches (MSW, LSW) or the control register, depends on the

address bits A1 and A0. NLDAC low updates the DAC with the value in the holding latch, see Figure 7.

NLDAC is an asynchronous input and can be held low, if a synchronous update is not necessary.

Alternatively, the RLDAC bit of the control register can be used to synchonously update the DAC latch via

software control, see Figure 8.

D[0-7]

A[0-1]

NCS

NWE

NLDAC

X

MSW

LSW

X

X

0

1

X

X

Figure 7 Example of a Complete Write Cycle Using NLDAC to Update the DAC

D[0-7]

A[0-1]

NCS

NWE

NLDAC

X

MSW

LSW

X

0

1

X

Control

X

X

X

3

X

X

Figure 8 Example of a Complete Write Cycle Using the Control Word to Update the DAC. If NLDAC is held low as shown

in Figure 8, latch will be transparent. This assumes that the RLDAC control register bit is low at the start and is written high on

the final write.