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WM8191 数据表(PDF) 8 Page - Wolfson Microelectronics plc |
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WM8191 数据表(HTML) 8 Page - Wolfson Microelectronics plc |
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8 / 27 page ![]() WM8191 Advanced Information WOLFSON MICROELECTRONICS LTD AI Rev 3.1 April 2001 8 OEB OP[13:0] t PZE Hi-Z t PEZ Hi-Z Figure 3 Output Data Enable Timing Test Conditions AVDD1 = AVDD2 = DVDD1 = 4.75 to 5.25V, DVDD2 = DVDD3 = 2.97 to 3.63V, AGND = DGND = 0V, TA = 0 to 70 °C, MCLK = 12MHz unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Output propagation delay tPD IOH = 1mA, IOL = 1mA 75 ns Output enable time tPZE 50 ns Output disable time tPEZ 25 ns SERIAL INTERFACE Figure 4 Serial Interface Timing Test Conditions AVDD1 = AVDD2 = DVDD1 = 4.75 to 5.25V, DVDD2 = DVDD3 = 2.97 to 3.63V, AGND = DGND = 0V, TA = 0 to 70 °C, MCLK = 12MHz unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS SCK period tSPER 83.3 ns SCK high tSCKH 37.5 ns SCK low tSCKL 37.5 ns SDI set-up time tSSU 10 ns SDI hold time tSH 10 ns SCK to SEN set-up time tSCE 20 ns SEN to SCK set-up time tSEC 20 ns SEN pulse width tSEW 50 ns SEN low to SDO = Register data tSERD 35 ns SCK low to SDO = Register data tSCRD 35 ns SCK low to SDO = ADC data tSCADC 25 ns Note: Parameters are measured at 50% of the rising/falling edge. SCK SDI SEN SDO t SPER t SCKL t SCKH t SSU t SH t SCE t SEW t SEC t SERD t SCRD MSB LSB t SCRDZ ADC DATA ADC DATA REGISTER DATA |
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