Advanced Information

WM8191

WOLFSON MICROELECTRONICS LTD

AI Rev 3.1 April 2001

13

MCLK

VSMP

VS

R

R

R

R

Figure 10 Reset Sample and Clamp Timing

For CIS type sensor signals, non-CDS processing is used. In this case, the video level is processed

with respect to the voltage on pin VRLC/VBIAS, generated internally or externally as described

this mode.

OFFSET ADJUST AND PROGRAMMABLE GAIN

The output from the CDS block is a differential signal, which is added to the output of an 8-bit offset

DAC to compensate for offsets and then amplified by an 8-bit PGA. The gain and offset for each

channel are independently programmable by writing to control bits DAC[7:0] and PGA[7:0].

In colour line-by-line mode the gain and offset coefficients for each colour can be multiplexed in order

(Red

→ Green → Blue → Red…) by pulsing the ACYC/RLC pin, or controlled via the FME,

ACYCNRLC and INTM[1:0] bits. Refer to the Line-by-Line Operation section for more details.

ADC INPUT BLACK LEVEL ADJUST

The output from the PGA must be offset to match the full-scale range of the ADC. For negative-going

input signals, a black level (zero differential) output from the PGA should be offset to the top of the

ADC range. For positive going input signal the black level should be offset to the bottom of the ADC

range. This is achieved by writing to control bits PGAFS[1:0].

OVERALL SIGNAL FLOW SUMMARY

Figure 11 represents the processing of the video signal through the WM8191.

V

RESET

V

VRLC

V

3

CDS = 1

CDS = 0

RLCEXT=1

260mV*(DAC[7:0]-127.5)/127.5

analog

-

X

+

+

V

OP[13:0]

D

1

digital

ADC BLOCK

PGA

BLOCK

OFFSET DAC

BLOCK

INPUT

SAMPLING

BLOCK

D

2

CDS, RLCEXT,RLCV[3:0], DAC[7:0],

PGA[7:0], PGAFS[1:0] and INVOP are set

by programming internal control registers.

CDS = 1 for CDS, 0 for non-CDS

V

V

V

V

IN

x (16383/V

+0

if PGAFS[1:0]=11

+16383 if PGAFS[1:0]=10

+8191 if PGAFS[1:0]=0x

PGA gain

A = 208/(283-PGA[7:0])

OUTPUT

INVERT

BLOCK

D2 = D1 if INVOP = 0

D2 = 16383-D1 if INVOP = 1

Offset

DAC

RLC

DAC

+

V

2

V

1

RLCEXT=0

Figure 11 Overall Signal Flow